Leveraging Thermally-Aware Chiplet Organization in 2.5D Systems to Reclaim Dark Silicon
Furkan Eris1,a, Ajay Joshi1,b, Andrew B. Kahng2, Yenai Ma1,c, Saiful Mojumder1,d and Tiansheng Zhang1,e
1Boston University, Boston, MA, USA
afe@bu.edu
bjoshi@bu.edu
cyenai@bu.edu
dmsam@bu.edu
etszhang@bu.edu
2UC San Diego, La Jolla, CA, USA
abk@cs.ucsd.edu
ABSTRACT
As on‐chip power densities of manycore systems continue to increase, one cannot simultaneously run all the cores due to thermal constraints. This phenomenon, known as the 'dark silicon' problem, leads to inactive regions on the chip and limits the performance of manycore systems. This paper proposes to reclaim dark silicon through a thermally‐aware chiplet organization technique in 2.5D manycore systems. The proposed technique adjusts the interposer size and the spacing between adjacent chiplets to reduce the peak temperature of the overall system. In this way, a system can operate with a larger number of active cores at a higher frequency without violating thermal constraints, thereby achieving higher performance. To determine the chiplet organization that jointly maximizes performance and minimizes manufacturing cost, we formulate and solve an optimization problem that considers temperature and interposer size constraints of 2.5D systems. We design a multi‐start greedy approach to find (near-)optimal solutions efficiently. Our analysis demonstrates that by using our proposed technique, an optimized 2.5D manycore system improves performance by 41% and 16% on average and by up to 87% and 39% for temperature thresholds of 85oC and 105oC, respectively, compared to a traditional single‐chip system at the same manufacturing cost. When maintaining the same performance as an equivalent single‐chip system, our approach is able to reduce the 2.5D system manufacturing cost by 36%.
