LARS: Logically Adaptable Retention Time STT‐RAM Cache for Embedded Systems
Kyle Kuana and Tosiron Adegbijab
University of Arizona, Tucson, AZ, USA
ackkuan@email.arizona.edu
btosiron@email.arizona.edu
ABSTRACT
STT-RAMs have been studied as a promising alternative to SRAMs in embedded systems' caches and main memories. STT‐RAMs are attractive due to their low leakage power and high density; STT‐RAMs, however, also have drawbacks of long write latency and high dynamic write energy. A popular solution to this drawback relaxes the retention time to lower both write latency and energy, and uses a dynamic refresh scheme that refreshes data blocks to prevent them from prematurely expiring. However, the refreshes can incur overheads, thus limiting optimization potential. In addition, this solution only provides a single retention time, and cannot adapt to applications' variable retention time requirements. In this paper, we propose LARS (Logically Adaptable Retention Time STT‐RAM) cache as a viable alternative for reducing the write energy and latency. LARS cache comprises of multiple STT‐RAM units with different retention times, with only one unit on at a given time. LARS dynamically determines which STT‐RAM unit to power on during runtime, based on executing applications' needs. Our experiments show that LARS cache is low‐overhead, and can reduce the average energy and latency by 35.8% and 13.2%, respectively, as compared to the dynamic refresh scheme.
Keywords: Spin‐Transfer Torque RAM (STT-RAM) cache, configurable memory, low‐power embedded systems, adaptable hardware, retention time.
