Optimizing Power-Accuracy trade-off in Approximate Adders
Celia Da, Vinita Vasudevanb and Nitin Chandrachoodanc
Department Electrical Engineering, Indian Institute of Technology Madras Chennai, India
aee13d003@ee.iitm.ac.in
bvinita@ee.iitm.ac.in
cnitin@ee.iitm.ac.in
ABSTRACT
Approximate circuit design has gained significance in recent years targeting applications like media processing where full accuracy is not required. In this paper, we propose an approximate adder in which the approximate part of the sum is obtained by finding a single optimal level that minimises the mean error distance. Therefore hardware needed for the approximate part computation can be removed, which effectively results in very low power consumption. We compare the proposed adder with various approximate adders in the literature in terms of power and accuracy metrics. The power savings of our adder is shown to be 17% to 55% more than power savings of the existing approximate adders over a significant range of accuracy values. Further, in an image addition application, this adder is shown to provide the best trade-off between PSNR and power.
Keywords: Approximate adder, Low power, Accuracy, A rchitectural approximation.
