A Cross‐layer Adaptive Approach for Performance and Power Optimization in STT-MRAM
Nour Sayeda, Rajendra Bishnoib, Fabian Oborilc and Mehdi B. Tahoorid
Karlsruhe Institute of Technology (KIT) Karlsruhe, Germany
anour.sayed@kit.edu
brajendra.bishnoi@kit.edu
cfabian.oboril@kit.edu
dmehdi.tahoori@kit.edu
ABSTRACT
Spin Transfer Torque Magnetic Random Access Memory (STT‐MRAM) is a promising candidate as a universal on‐chip memory technology due to non‐volatility, high density and scalability. However, high write energy and latency are major challenges in this memory technology due to the asymmetry and stochastic nature of the write operation. Typically, the write current is set for the minimum energy point, which can further impact the write latency. To mitigate these issues, we propose an adaptive write current scaling technique that adjusts the write current, and hence the write latency and energy based on the performance needs at run‐time. Using this technique, optimal energy and performance points for write current are obtained using detailed device and system level analysis. Furthermore, we use runtime adaptation of write current by predicting the write access rate for the next execution phase. We evaluate the efficiency of the proposed approach on SPEC2000 applications for STT-MRAM-based L1 and L2- cache levels. The results show that the effective write latency of L1 and L2 is reduced by 52.4% and 55.7% with 7.6% and 1.4% area overheads, respectively, corresponding to the overall system performance optimization of 15.5% while the total memory energy consumption is increasing by only 3.2%.
