An Efficient NBTI‐Aware Wake‐Up Strategy for Power‐Gated Designs
Kun‐Wei Chiu1,a, Yu-Guang Chen2 and Ing‐Chao Lin1,b
1National Cheng Kung University, Tainan, Taiwan
ad9372199@hotmail.com,
bandyygchen@saturn.yzu.edu.tw
2Yuan Ze University, Taoyuan, Taiwan
iclin@mail.ncku.edu.tw
ABSTRACT
The wake-up process of a power‐gated design may induce an excessive surge current and threaten the signal integrity. A proper wake-up sequence should be carefully designed to avoid surge current violations. On the other hand, PMOS sleep transistors may suffer from the negative‐bias temperature instability (NBTI) effect which results in decreased driving current. Conventional wake‐up sequence decision approaches do not consider the NBTI effect, which may result in a longer or unacceptable wake‐up time after circuit aging. Therefore, in this paper, we propose a novel NBTI‐aware wake‐up strategy to reduce the average wake‐up time within a circuit lifetime. Our strategy first finds a set of proper wake‐up sequences for different aging scenarios (i.e. after a certain period of aging), and then dynamically reconfigures the wake‐up sequences at runtime. The experimental results show that compared to a traditional fixed wake-up sequence approach, our strategy can reduce average wake‐up time by as much as 45.04% with only 3.7% extra area overhead for the reconfiguration structure.
Keywords: Power gating, Wake-up sequence, NBTI.
