Program Error Rate-based Wear Leveling for NAND Flash Memory
Xin Shi1,a, Fei Wu1,2,b,c, Shunzhuo Wang1,d, Changsheng Xie1,e and Zhonghai Lu2,f
1Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, China
2KTH Royal Institute of Technology, Sweden
ashixin@hust.edu.cn
bFei Wu@hust.edu.cn
cwufei@hust.edu.cn
dwangshunzhuo@hust.edu.cn
ecs_xie@hust.edu.cn
fzhonghai@kth.se
ABSTRACT
Wear leveling scheme has became a fundamental issue in the design of Solid State Disk (SSD) based on NAND Flash memory. Existing schemes aim to equalize the number of programming/erase (P/E) cycles and memory raw bit error rates (BER) among all the flash blocks. However, due to fabrication process variation, different blocks of the same flash chip usually have largely different endurance in terms of BER and program error rate (PER). Such conventional design cannot obtain the wear status of flash blocks precisely. This paper proposes PERWL, an efficient PER‐based wear leveling scheme that uses PER statistics as the measurement of flash block wear‐out pace, and performs block data swapping to improve the wear leveling efficiency. In our evaluation with four realistic workloads, PERbased wear leveling scheme can achieve 17% and 9% variance of program error rate reduction, 8% and 3% program error rate reduction with 5% and 2% system performance degradation when compared to two state‐of‐the‐art wear leveling schemes on average.
