Improvements to Boolean Resynthesis
Luca Amarú1, Mathias Soeken2, Patrick Vuillod1, Jiong Luo1, Alan Mishchenko3, Janet Olson1, Robert Brayton3 and Giovanni De Micheli2
1Synopsys Inc., Design Group, Sunnyvale, California, USA
2Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
3Department of EECS, UC Berkeley, Berkeley, California, USA
ABSTRACT
In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima. Boolean methods rely on complete functional properties of a logic circuit, preferably including don't care information. Computationally expensive engines such as truth tables, SAT and binary decision diagrams are required to gather such properties. The choice of the engine determines the scalability of Boolean resynthesis. In this paper, we present improvements to Boolean resynthesis, enabling more optimization opportunities to be found at the same or smaller runtime cost as compared to state‐of‐the‐art methods. Our contributions include (i) a theory of Boolean filtering to drastically reduce the number of gates processed and still retain all possible optimization opportunities, (ii) a weaker notion of maximum set of permissible functions, which can be computed efficiently via truth tables, (iii) a generalized refactoring engine that supports multiple representation forms, and (iv) a practical Boolean resynthesis flow, which combines the techniques proposed so far. Using our Boolean resynthesis on the EPFL benchmarks, we improve 10 of the best known area results in the synthesis competition. Embedded in a commercial EDA flow for ASICs, the Boolean resynthesis flow reduces the area by ‐2.67% and total negative slack by ‐5.48%, after physical implementation, at negligible runtime cost.
