ADAM: Architecture for Write DisturbAnce Mitigation in Scaled Phase Change Memory
Shivam Swamia and Kartik Mohanramb
University of Pittsburgh, PA
ashs173@pitt.edu
bkartik.mohanram@gmail.com
ABSTRACT
With technology scaling, phase change memory (PCM) has become highly vulnerable to write disturbance (WD) errors. A PCM WD error occurs when a cell write dissipates heat to idle cells in the same/adjacent word lines (WLs), disturbing the states of those cells. Whereas state‐of‐the‐art solutions, e.g., data insulation (DIN) and super dense PCM (SD-PCM), have successfully addressed WL PCM WD errors, reducing (i) bit line (BL) WD errors and (ii) the performance penalties of aggregate (WL+BL) WD error recovery remain areas of active research and development. Architecture for Write DisturbAnce Mitigation, ADAM, is a low cost, high performance pattern‐based data compression and alignment solution to reduce the aggregate (WL+BL) WD error rate in PCM. At no impact to inter‐cell spacing, ADAM increases the lateral separation between the cells storing useful data in adjacent WLs, ensuring that the heat dissipated to adjacent WLs minimally impacts the cells storing useful data. For one compression tag bit per 512‐bit cache line, ADAM provides an effective solution to reduce the number of WL and BL cells vulnerable to WD errors. ADAM also integrates a novel Deferred WD Correction scheme, DEFT, that opportunistically defers latency‐intensive WD error recovery of cached data in the adjacent WLs without impacting memory reliability. ADAM is evaluated on single‐/multi‐level cell (SLC/MLC) PCM using the SPEC CPU2006 benchmarks. Re‐ sults for SLC (MLC) PCM show that in comparison to state‐of‐the‐ art SD‐PCM, ADAM reduces the aggregate WD error rate by 32% (60%); this translates to a 50%(61%) reduction in error correction energy and a 7% (15%) improvement in system performance.
