Multi‐Bit Non‐Volatile Spintronic Flip‐Flop
Christopher Müncha, Rajendra Bishnoib and Mehdi B. Tahooric
Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
achristopher.muench@student.kit.edu
brajendra.bishnoi@kit.edu
cmehdi.tahoori@kit.edu
ABSTRACT
As leakage increases proportionally with the technology downscaling, it becomes extremely challenging to manage to meet the total power budget. This is because, CMOS‐based logic blocks can not be completely power‐gated as their flip‐flops always require a retention supply to hold the system states. Alternatively, their data can be stored in a separate memory during the standby mode, however, that results in a huge area and energy overhead. Spin Transfer Torque (STT) based nonvolatile flip-flops can offer normally‐off/instant‐on computing features to reduce leakage by complete power shut‐down without the need to transfer and restore system states separately. The non‐volatile component of such flip‐flops can be easily shared for the overall design optimizations. In this paper, we design a unique multi‐bit non‐volatile flip‐flop architecture using STT devices to reduce the area and energy costs associated with nonvolatile components. This architecture is developed based on the resource sharing principle using a custom design that enables the optimization for the area and energy consumption. Moreover, we have developed a framework in which we have replaced the conventional neighbor flipflops in the layout with our proposed multi‐bit non‐volatile designs. Results show that using our multi‐bit flip‐flop architecture, we improve the system-level area and energy by 26% and 14% in average, respectively, compared to the standard single‐bit non‐volatile flip‐flop design.
