A Physical Synthesis Flow for Early Technology Evaluation of Silicon Nanowire based Reconfigurable FETs

Shubham Rai1,3, Ansh Rupani1,5, Dennis Walter2, Michael Raitza1,3, Andrè Heinzig3, Tim Baldauf3,4, Jens Trommer6, Christian Mayr2, Walter M. Weber6,3 and Akash Kumar1,3
1Chair For Processor Design
2Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics
3CfAED Technische Universität Dresden, Dresden, Germany
4HTW-Dresden, Dresden, Germany
5BITS Pilani, India
6Namlab gGmbH, Dresden, Germany

ABSTRACT


Silicon Nanowire (SiNW) based reconfigurable field effect transistors (RFETs) provide an additional gate terminal called the program gate which gives the freedom of programming p‐type or n‐type functionality for the same device at runtime. This enables the circuit designers to pack more functionality per computational unit. This saves processing costs as only one device type is required, and no doping and associated lithography steps are needed for this technology. In this paper, we present a complete design flow including both logic and physical synthesis for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors. We show that in the first of its kind comparison, for these fully symmetrical reconfigurable transistors, the area after placement and routing for SiNW based circuits is 17% more than that of CMOS for MCNC benchmarks. Further, we discuss areas of improvement for obtaining better area results from the SiNW based RFETs from a fabrication and technology point of view. The future use of self‐aligned techniques to structure two independent gates within a smaller pitch holds the promise of substantial area reduction.


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