Technology Mapping Flow for Emerging Reconfigurable Silicon Nanowire Transistors
Shubham Raia, Michael Raitzab and Akash Kumarc
Chair For Processor Design, CfAED, Technische Universität Dresden, Dresden, Germany
aShubham.Rai@tu-dresden.de
bMichael.Raitza@tu-dresden.de
cAkash.Kumar@tu-dresden.de
ABSTRACT
Efficient circuit designs can make use of ambipolar nature of silicon nanowire (SiNW) over CMOS. Conventional circuit Design‐Flow fails to use this inherent functional flexibility as CMOS based mapping considers a single logical output from logic gates. To address this, we propose an area‐optimized technology mapping which uses this innate reconfigurability, offered by SiNW transistors for efficient circuit designs. To enable this objective, we use higher order functions (HOF) to encapsulate this extended functionality. Additionally, the electrical properties of SiNW allow us to take advantage of the available inverted forms of fan‐ins for additional savings of area for XOR logic family. Experimental results using our technology mapping show that area of SiNW based logic design is less by an average of 18:38% as compared to CMOS flow for complete MCNC benchmarks suite. Further, we evaluate our flow for both reconfigurability‐aware and static layout for SiNW based logic gates. The whole flow including the new SiNW based genlib and the modified ABC tool is made available under open source license to enable further research for any kind of emerging ambipolar transistors.
