Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee
Yung‐An Lai1, Chia‐Chun Lin1, Chia‐Cheng Wu1, Yung‐Chih Chen2 and Chun-Yao Wang1
1National Tsing Hua University, Hsincu, Taiwan, R.O.C.
2Yuan Ze University, Chungli, Taiwan, R.O.C.
ABSTRACT
Recently, Threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks. Approximate computing is a new design paradigm that focuses on error‐tolerant applications, e.g., machine learning or pattern recognition. In this paper, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost‐efficient approximate threshold logic circuits with an error rate guarantee. We conduct experiments on IWLS 2005 benchmarks. The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark. For a 5% error rate constraint, the circuit cost can be reduced by up to 65%, and 22.8% on average. Compared with a naive method, our approach has a speedup of 2.42 under a 5% error rate constraint.
