Task Scheduling for Many‐Cores with S‐NUCA Caches
Anuj Pathaniaa and Jörg Henkel
Chair of Embedded System (CES), Karlsruhe Institute of Technology, Germany
aanuj.pathania@kit.edu
ABSTRACT
A many‐core processor may comprise a large number of processing cores on a single chip. The many‐core's last‐level shared cache can potentially be physically distributed alongside the cores in the form of cache banks connected through a Network on Chip (NoC). Static Non‐Uniform Cache Access (SNUCA) memory address mapping policy provides a scalable mechanism for providing the cores quick access to the entire last level cache. By design, S‐NUCA introduces a unique topology based performance heterogeneity and we introduce a scheduler that can exploit it. The proposed scheduler improves performance of the many‐core by 9.93% in comparison to a state‐of‐the‐art generic many‐core scheduler with minimal run‐time overheads.
