Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement
Taehyun Kwon1,a, Muhammad Imran2,c, Jung Min You2,d and Joon-Sung Yang1,b
1System LSI Division, Samsung Electronics, Korea
ath.kwon@skku.edu
bjs.yang@skku.edu
2Sungkyunkwan University, Suwon, Korea
cimran@skku.edu
dyugura@skku.edu
ABSTRACT
Conventional DRAM and flash memory are reaching their scaling limits thus motivating research in various emerging memory technologies as a potential replacement. Among these, phase change memory (PCM) has received considerable attention owing to its high scalability and multi‐level cell (MLC) operation for high storage density. However, due to the resistance drift over time, the soft error rate in MLC PCM is high. Additionally, the iterative programming in MLC negatively impacts performance and cell endurance. The conventional methods to overcome the drift problem incur large overheads, impact memory lifetime and are inadequate in terms of acceptable soft error rate (SER). In this paper, we propose a new PCM memory architecture with heterogeneous PCM arrays to increase reliability, performance and lifetime. The basic storage unit in the proposed architecture consists of two single‐level cells (SLCs) and one four‐level cell (4LC). Using the reduced number of 4LCs compared to conventional homogeneous 4LC PCM arrays, the drift‐induced error rate is considerably reduced. By alternating each cell operation between SLC and 4LC over time, the overall lifetime can also be significantly enhanced. The proposed architecture achieves up to 105 times lower soft error rate with considerably less ECC overhead. With simple ECC scheme, about 22% performance improvement is achieved and additionally, the overall lifetime is also enhanced by about 57%.
Keywords: Emerging memories, Endurance, Multi‐level cell, Heterogeneous cell storage, Phase change memory (PCM), Resistance drift, Reliability.
