WALL: A Writeback‐Aware LLC Management for PCM‐based Main Memory Systems
Bahareh Pourshirazi1,a, Majed Valad Beigi2,c, Zhichun Zhu1,b and Gokhan Memik2,d
1University of Illinois at Chicago, Chicago, USA
abpours2@uic.edu
bzzhu@uic.edu
2Northwestern University, Evanston, USA
cmajed.beigi@northwestern.edu
dmemik@eecs.northwestern.edu
ABSTRACT
In this paper, we propose WALL, a novel write back aware LLC management scheme to reduce the number of LLC write backs and consequently improve performance, energy efficiency, and lifetime of a PCM‐based main memory system. First, we investigate the write back behavior of LLC sets and show that write backs are not uniformly distributed among sets; some sets observe much higher write back rates than others. We then propose a write back‐aware set‐balancing mechanism, which employs the underutilized LLC sets with few write backs as an auxiliary storage for storing the evicted dirty lines of sets with frequent write backs. We also propose a simple and effective write back‐aware replacement policy to avoid the eviction of the write back blocks that are highly reused after being evicted from the cache. Our experimental results show that WALL achieves an average of 26.6% reduction in the total number of LLC write backs, compared to the baseline scheme, which uses the LRU replacement policy. As a result, WALL can reduce the memory energy consumption by 19.2% and enhance PCM lifetime by 1.25∼, on average, on an 8‐core system with a 4GB PCM main memory, running memory intensive applications.
Keywords: Phace Change Memory, Write Endurance, Energy Consumption, Performance, Last Level Cache.
