Sensei: An Area-Reduction Advisor for FPGA High‐Level Synthesis
Hsuan Hsiaoa and Jason H. Andersonb
University of Toronto, Toronto, Ontario, Canada
ajulie.hsiao@mail.utoronto.ca
bjanders@ece.utoronto.ca
ABSTRACT
High‐level synthesis (HLS) provides an easy‐to‐use abstraction for designing hardware circuits. However, standard data types in high‐level languages are over provisioned for typical applications, incurring extra area since the underlying FPGA hardware can support arbitrary bit widths. This area inefficiency can be overcome by enabling the use of arbitrary‐width data types at the source code level. However, this requires that HLS users spend time and effort on examining all program variables and quantifying their area impact, which can be intractable especially with large, complex programs and time‐consuming synthesis. We propose Sensei, an advisor that predicts the post-synthesis area savings brought about by reducing bitwidth and presents users with a ranking of program variables and their area impact. Equipped with a convolutional neural network (CNN)‐based predictor, Sensei achieves high area‐prediction accuracy and enables rapid exploration of area‐saving opportunities.
