URECA: A Compiler Solution to Manage Unified Register File for CGRAs
Shail Davea, Mahesh Balasubramanianb and Aviral Shrivastavac
Compiler Microarchitecture Lab, Arizona State University, Tempe, AZ
ashail.dave@asu.edu
bmbalasu2@asu.edu
caviral.shrivastava@asu.edu
ABSTRACT
Coarse‐grained reconfigurable array (CGRA) is a promising solution to accelerate loops featuring loop‐carried dependencies or low trip‐counts. One challenge in compiling for CGRAs is to efficiently manage both recurring (repeatedly written and read) and nonrecurring (read‐only) variables of loops. Although prior works manage recurring variables in rotating register file (RF), they access the nonrecurring variables through the on‐chip memory. It increases memory accesses and degrades the performance. Alternatively, both the variables can be managed in separate rotating and nonrotating RFs. But, it increases code size and effective utilization of the registers becomes challenging. Instead, this paper proposes URECA, a compiler solution to manage the variables in a single nonrotating RF. During mapping loop operations on CGRA, the compiler allocates necessary registers and splits RF in rotating and nonrotating parts. It also pre‐loads read‐only values in the unified RF, which are then directly accessed at run‐time. Evaluating compute‐intensive benchmarks from MiBench show that URECA provides a geomean speedup of 11.41x over sequential loop execution. It improves the loop acceleration through CGRAs by 1.74x at 32% reduced energy consumption over state‐of‐the‐art.
