DATE 2012, Table of Contents

DATE 2012 AUTHOR INDEX

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

Aasaraai, K: Toward Virtualizing Branch Direction Prediction [p. 455]
Abate, F: Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Abdallah, L: Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Abed, I S: Double-Patterning Friendly Grid-Based Detailed Routing with Online Conflict Resolution [p. 1475]
Abelein, U: Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Abellan, J L: Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Aboushady, H: Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Abraham, J A: On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Acacio, M E: Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Acquaviva, A: Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Adlkofer, H: Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Adve, S V: CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Afzali-Kusha, A: An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Ahn, J H: CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Ahopelto, J: Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Aisopos, K: PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Akbari, S: AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Akesson, B: DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]; Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Aksanli, B: Benefits of Green Energy and Proportionality in High Speed Wide Area Networks Connecting Data Centers [p. 175]
Aksoy, L: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Aktouf, O-E-K: Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Al-Faruque, M A: Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]; Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Al-Hashimi, B M: Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Almeroth, B: Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Aloufi, M: Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Altet, J: Testing RF Circuits with True Non-Intrusive Built-In Sensors [p. 1090]
Alvarez-Herault, J: Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Amara, A: Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design Optimization [p. 93]
Ambrose, A: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up [p. 1283]
Anagnostopoulos, I: A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Anderson, J: Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Anghel, L: Design for Test and Reliability in Ultimate CMOS [p. 677]
Anis, M: AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Annaswamy, A: Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Appleton, E: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Aridhi, H: Towards Improving Simulation of Analog Circuits Using Model Order Reduction [p. 1337]
Ascheid, G: Hybrid Simulation for Extensible Processor Cores [p. 288]
Ashouei, M: Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Atienza, D: Thermal Balancing of Liquid-Cooled 3D-MPSoCs Using Channel Modulation [p. 599]; Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]; A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Aubert, A: Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Augustine, C: A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach [p. 1443]
Austin, T: CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Avresky, D: Design for Test and Reliability in Ultimate CMOS [p. 677]
Axer, P: Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Ayoub, R: TempoMP: Integrated Prediction and Management of Temperature in Heterogeneous MPSoCs [p. 593]
Azevedo, J: Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]

Babayan, E: Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Bahl, S: EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Bainbridge, W J: Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Bamakhrama, M A: A Methodology for Automated Design of Hard-Real-Time Embedded Streaming Systems [p. 941]
Banerjee, A: Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]; Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Baronti, F: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Bartolini, A: Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]
Bartzas, A: A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Basten, T: Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Basu, S: Correct-by-Construction Multi-Component SoC Design [p. 647]
Bathen, L A D: VaMV: Variability-aware Memory Virtualization [p. 284]; 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]
Battezzati, N: SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Bauer, L: Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]; Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Baumanns, S: Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Beaumont, M: SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Becker, B: On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]; Verification of Partial Designs Using Incremental QBF Solving [p. 623]
Becker, J: A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]; On Demand Dependent Deactivation of Automotive ECUs [p. 69]; Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Becker, M: MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Belta, C: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Benini, L: Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]; Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]; Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]; Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]; A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]; P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]; Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]; An Energy Efficient DRAM Subsystem for 3D Integrated SoCs [p. 1138]
Benkner, S: Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Benoit, P: Amplitude Demodulation-based EM Analysis of Different RSA Implementations [p. 1167]
Berangi, R: AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Berkelaar, M: Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Beroulle, V: Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Bertacco, V: Approximating Checkers for Simulation Acceleration [p. 153]; CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Bertels, K: Using Multi-objective Design Space Exploration to Enable Run-time Resource Management for Reconfigurable Architectures [p. 1379]
Bertozzi, D: Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]; A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Bertrand, D: Challenges and New Trends in Probabilistic Timing Analysis [p. 810]
Beste, M: Layout-Driven Robustness Analysis for Misaligned Carbon Nanotubes in CNTFET-based Standard Cells [p. 1609]
Bhardwaj, K: An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Bhatia, S: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Bi, X: Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
Bittner, K: Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Blech, J O: Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Blom, H: Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Bocca, A: Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Bolchini, C: An Adaptive Approach for Online Fault Management in Many-Core Architectures [p. 1429]
Bombieri, N: FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Bonamy, R: UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Bonilla, E: Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Borde, E: Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Bordoloi, U D: A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Bortolotti, D: Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Bose, P: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Bosio, A: Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Bovington, J: Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Bowman, K: Design for Test and Reliability in Ultimate CMOS [p. 677]
Bozga, M: State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Brachtendorf, H G: Simulation of the Steady State of Oscillators in the Time Domain [p. 1355]
Brandl, M: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Brault, J -M: NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Brayton, R: Mapping into LUT Structures [p. 1579]
Brayton, R K: Scalable Progress Verification in Credit-Based Flow-Control Systems [p. 905]
Brenner, U: VLSI Legalization with Minimum Perturbation by Iterative Augmentation [p. 1385]
Bringmann, O: Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]; Optimal Energy Management and Recovery for FEV [p. 683]; Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Brisk, P: Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Brockman, J B.: CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Brokalakis, A: An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Bruening, A: Memristor Technology in Future Electronic System Design [p. 592]; Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Brunelli, D: Smart Power Unit with Ultra Low Power Radio Trigger Capabilities for Wireless Sensor Networks [p. 75]
Buckl, C: Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]
Burg, A: Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Burgio, P: Fast and Lightweight Support for Nested Parallelism on Cluster-Based Embedded Many-Cores [p. 105]
Buyuktosunoglu, A: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]

Cai, Y: Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Calazans, N: An Accurate Single Event Effect Digital Design Flow for Reliable System Level Design [p. 224]
Calimera, A: IR-Drop Analysis of Graphene-Based Power Distribution Networks [p. 81]; Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Campagna, S: An Hybrid Architecture to Detect Transient Faults in Microprocessors: An Experimental Validation [p. 1433]
Campbell, S A: Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Camposano, R: Moore Meets Maxwell [p. 1275]
Canedo, A: Intelligent and Collaborative Embedded Computing in Automation Engineering [p. 344]; Towards Parallel Execution of IEC 61131 Industrial Cyber-Physical Systems Applications [p. 554]
Carloni, L P: Compositional System-Level Design Exploration with Planning of High-Level Synthesis [p. 641]
Carr, S B: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Catthoor, F: Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]; A Hybrid HW-SW Approach for Intermittent Error Mitigation in Streaming-Based Embedded Systems [p. 1110]
Cenni, F: Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Cha, B: Salvaging Chips with Caches beyond Repair [p. 1263]
Chakrabarty, K: Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]; Test Pin Count Reduction for NoC-based Test Delivery in Multicore SOCs [p. 787]; A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Chakraborty, K: An MILP-Based Aging-Aware Routing Algorithm for NoCs [p. 326]
Chakraborty, S: Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]; Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chandrasekar, K: A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Chang, K-H: RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Chang, L-P: Dual Greedy: Adaptive Garbage Collection for Page-Mapping Solid-State Disks [p. 117]
Chang, N: Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; Embedded Systems and Software Challenges in Electric Vehicles [p. 424]; State of Health Aware Charge Management in Hybrid Electrical Energy Storage Systems [p. 1060]
Chang, S-C: A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chang, Y-W: Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Chao, H-L: Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chatterjee, D: Approximating Checkers for Simulation Acceleration [p. 153]
Chaturvedi, S: Static Analysis of Asynchronous Clock Domain Crossings [p. 1122]
Chatziparaskevas, G: An FPGA-based Parallel Processor for Black-Scholes Option Pricing Using Finite Differences Schemes [p. 709]
Chen, C: Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]; Mapping into LUT Structures [p. 1579]
Chen, C-L: Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Chen, D: Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Chen, H: QBF-Based Boolean Function Bi-Decomposition [p. 816]; Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Chen, H-M: Agglomerative-Based Flip-Flop Merging with Signal Wirelength Optimization [p. 1391]; On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, J: A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Chen, J-J: Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Chen, K: CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Chen, L: Online Scheduling for Multi-Core Shared Reconfigurable Fabric [p. 582]; CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Chen, M-L: On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, Q: Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]; Characterization of the Bistable Ring PUF [p. 1459]
Chen, S-H: On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Chen, S-J: Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, W: Out-of-Order Parallel Simulation for ESL Design [p. 141]
Chen, Y: 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]; Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]; Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]; Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Chen, Y-C: A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chen, Y-R: Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Chen, Y-T: Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
Cheng, K-T: Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Cheng, X: Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
Cherkaoui, A: Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Chian, M: New Foundry Models - Accelerations in Transformations of the Semiconductor Industry [p. 2]
Chiang, M-F: A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors [p. 1519]
Chillet, D: UPaRC -- Ultra-Fast Power-aware Reconfiguration Controller [p. 1373]
Choi, K: State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Chong, S: Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Chou, C-N: Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Chou, H-M: A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Chou, H-Z: RTL Analysis and Modifications for Improving At-speed Test [p. 400]
Choudhary, A: Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Chua, L O: Memristor Technology in Future Electronic System Design [p. 592]
Chuang, Y-L: Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]
Cifrain, M: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Clavier, L: Holistic Modeling of Embedded Systems with Multi-Discipline Feedback: Application to a Precollision Mitigation Braking System [p. 739]
Colazzo, S: SURF Algorithm in FPGA: A Novel Architecture for High Demanding Industrial Applications [p. 161]
Condo, C: A Network-on-Chip-based Turbo/LDPC Decoder Architecture [p. 1525]
Cong, J: Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Constantin, J: Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Cordes, D: Multi-Objective Aware Extraction of Task-Level Parallelism Using Genetic Algorithms [p. 394]
Corporaal, H: Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]; Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Cosemans, S: Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Coskun, A K: Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]; Analysis and Runtime Management of 3D Systems with Stacked DRAM for Boosting Energy Efficiency [p. 611]; Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Costa, E: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Craninckx, J: Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Cristal, A: TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]
Csaba, G: Characterization of the Bistable Ring PUF [p. 1459]
Cucuccio, A: Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Cui, T: Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Cui, X: Modeling and Testing of Interference Faults in the Nano NAND Flash Memory [p. 527]
Cui, Z: Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Cullmann, C: Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Cupaiuolo, T: A Flexible and Fast Software Implementation of the FFT on the BPE Platform [p. 1467]
Czutro, A: On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]

Daghar, A: Verifying Jitter in an Analog and Mixed Signal Design Using Dynamic Time Warping [p. 1413]
Damavandpeyma, M: Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Daneshtalab, M: CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]
Dang, X: S/DC: A Storage and Energy Efficient Data Prefetcher [p. 461]
Danger, J-L: RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Daniel, L: An Efficient Framework for Passive Compact Dynamical Modeling of Multiport Linear Systems [p. 1203]
Darringer, J A: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Das, A: Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]; PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Das, S: PowerAdviser: An RTL Power Platform for Interactive Sequential Optimizations [p. 550]
Dasgupta, P: Formal Methods for Ranking Counterexamples through Assumption Mining [p. 911]
Dastgeer, U: Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
David, A: State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Davoodi, A: A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection [p. 1331]; Custom On-Chip Sensors for Post-Silicon Failing Path Isolation in the Presence of Process Variations [p. 1591]
De Jonghe, D: Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]; Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
De Micheli, G: Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]
De Smedt, B: Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
De, V: Design for Test and Reliability in Ultimate CMOS [p. 677]
Defo, G B G: MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]
Dehaene, W: Design of a Low-Energy Data Processing Architecture for WSN Nodes [p. 570]; Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Deniz, E: Verification Coverage of Embedded Multicore Applications [p. 252]
Densmore, D: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Desbarbieux, J-I: An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Dey, O: Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Di Carlo, S: A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Di Guglielmo, G: Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Guglielmo, L: Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]
Di Natale, M: Task Implementation of Synchronous Finite State Machines [p. 206]
Dilillo, L: Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Dimitrakopoulos, G: Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Doemer, R: Out-of-Order Parallel Simulation for ESL Design [p. 141]
Dogan, A Y: Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems [p. 988]
Dolinsky, U: Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Domic, A: Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Donno, M: Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
dos Santos, L C V: On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Dousti, M J: Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric [p. 840]
Drach, N: An Out-of-Order Superscalar Processor on FPGA: The ReOrder Buffer Design [p. 1549]
Drechsler, R: A Guiding Coverage Metric for Formal Verification [p. 617]; Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]; Debugging of Inconsistent UML/OCL Models [p. 1078]; Eliminating Invariants in UML/OCL Models [p. 1142]
Druml, N: Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Du, K: High Performance Reliable Variable Latency Carry Select Addition [p. 1257]
Duan, G: Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Dutt, N D: VaMV: Variability-aware Memory Virtualization [p. 284]; 3D-FlashMap: A Physical-Location-Aware Block Mapping Strategy for 3D NAND Flash Memory [p. 1307]

Ebeid, E: Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Ebrahimi, M: CATRA -Congestion Aware Trapezoid-based Routing Algorithm for On-Chip Networks [p. 320]; SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Edwards, D: Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Een, N: Mapping into LUT Structures [p. 1579]
Ejlali, A: SCFIT: A FPGA-based Fault Injection Technique for SEU Fault Model [p. 586]
Eklow, B: On Effective TSV Repair for 3D-Stacked ICs [p. 793]
Eles, P: Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]; A Scalable GPU-based Approach to Accelerate the Multiple-Choice Knapsack Problem [p. 1126]
Ellen, C: Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Enescu, F: Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Ernst, R: Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]; A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]; Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]; Optimizing Performance Analysis for Synchronous Dataflow Graphs with Shared Resources [p. 635]; Challenges and New Trends in Probabilistic Timing Analysis [p. 810]; Probabilistic Response Time Bound for CAN Messages with Arbitrary Deadlines [p. 1114]
Etzien, C: Automatic Transition Between Structural System Views in a Safety Relevant Embedded Systems Development Process [p. 820]
Eusse, J: Hybrid Simulation for Extensible Processor Cores [p. 288]

Fabiano, M: A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Fahmy, S: Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Fan, M: Neighbor-Aware Dynamic Thermal Management for Multi-core Platform [p. 187]; Harmonic Semi-Partitioned Scheduling for Fixed-Priority Real-Time Tasks on Multi-Core Platform [p. 503]
Fan, X: Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Fantechi, G: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fanucci, L: Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]; Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Fatemi, H: Sliding-Mode Control to Compensate PVT Variations in Dual Core Systems [p. 1048]
Fathy, M: AFRA: A Low Cost High Performance Reliable Routing for 3D Mesh NoCs [p. 332]
Faura, D: Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Fernandez, J: Design of a Collective Communication Infrastructure for Barrier Synchronization in Cluster-Based Nanoscale MPSoCs [p. 491]
Ferrari, A: Mechatronic System for Energy Efficiency in Bus Transport [p. 342]
Fesquet, L: Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Fettweis, G: Pathways to Servers of the Future - Highly Adaptive Energy Efficient Computing (HAEC) [p. 1161]; Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Figueras, J: Efficiency Evaluation of Parametric Failure Mitigation Techniques for Reliable SRAM Operation [p. 1343]
Fiorini, P: Predictive Control of Networked Control Systems over Differentiated Services Lossy Networks [p. 1245]
Firouzi, F: NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Fischer, V: Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs [p. 1325]
Flamand, E: P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Flores, P: Design of Low-Complexity Digital Finite Impulse Response Filters on FPGAs [p. 1197]
Fohler, G: On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Fradet, P: SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Franchi, E: Low-power Embedded System for Real-Time Correction of Fish-Eye Automotive Cameras [p. 340]
Fritz, G: Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Fu, X: CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Fuin, D: P2012: Building an Ecosystem for a Scalable, Modular and High-Efficiency Embedded Computing Accelerator [p. 983]
Fummi, F: Enabling Dynamic Assertion-based Verification of Embedded Software through Model-driven Design [p. 212]; MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution [p. 296]; FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]; Refinement of UML/MARTE Models for the Design of Networked Embedded Systems [p. 1072]
Furst, J-N: Quantifying the Impact of Frequency Scaling on the Energy Efficiency of the Single-Chip Cloud Computer [p. 181]

Gadkari, A: An Integrated Test Generation Tool for Enhanced Coverage of Simulink/Stateflow Models [p. 308]
Gall, H: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gamatie, A: Design of Streaming Applications on MPSoCs Using Abstract Clocks [p. 763]
Gan, J: Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Ganguly, R: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Ganta, D: ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gao, J: A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Gao, M: Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Gao, P: Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]
Garcia-Ortiz, A: Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]
Garside, J: Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches [p. 1495]
Garudadri, H: A Closed-loop System for Artifact Mitigation in Ambulatory Electrocardiogram Monitoring [p. 431]
Gatti, M: Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Gebhard, G: Hybrid Source-Level Simulation of Data Caches Using Abstract Cache Models [p. 376]
Geilen, M: Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]; Modeling Static-Order Schedules in Synchronous Dataflow Graphs [p. 775]
Genser, A: Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Gerdes, M: Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Ghodrat, M A: Optimization Intensive Energy Harvesting [p. 272]
Giegerich, M: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
Gielen, G: Hierarchical Analog Circuit Reliability Analysis Using Multivariate Nonlinear Regression and Active Learning Sample Selection [p. 745]; A Fast Analog Circuit Yield Estimation Method for Medium and High Dimensional Problems [p. 751]; Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]; Design of an Intrinsically-Linear Double- VCO-based ADC with 2nd-order Noise Shaping [p. 1215]; Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs [p. 1615]
Girard, P: Impact of Resistive-Open Defects on the Heat Current of TAS-MRAM Architectures [p. 532]
Girault, A: SPDF: A Schedulable Parametric Data-Flow MoC [p. 769]
Giusto, P: Using Timing Analysis for the Design of Future Switched Based Ethernet Automotive Networks [p. 57]
Givargis, T: MEDS: Mockup Electronic Data Sheets for Automated Testing of Cyber-Physical Systems Using Digital Mockups [p. 1417]
Glass, M: Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach [p. 276]
Goehringer, D: Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Goel, M: A High Performance Split-Radix FFT with Constant Geometry Architecture [p. 1537]
Goel, S K: EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Gol, E A: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Goldman, R: Investigating the Effects of Inverted Temperature Dependence (ITD) on Clock Distribution Networks [p. 165]
Gomony, M D: DRAM Selection and Configuration for Real-Time Mobile Systems [p. 51]
Gong, J: Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
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Goswami, D: Time-triggered Implementations of Mixed-Criticality Automotive Software [p. 1227]
Goswami, D: Timing Analysis of Cyber-Physical Applications for Hybrid Communication Protocols [p. 1233]
Graeb, H: ITRS 2011 Analog EDA Challenges and Approaches - Invited Paper [p. 1150]
Graef, M W M: Beyond CMOS - Benchmarking for Future Technologies [p. 129]
Grass, E: Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Grivet-Talocia, S: Moore Meets Maxwell [p. 1275]
Grosse, D: A Guiding Coverage Metric for Formal Verification [p. 617]
Grudnitsky, A: Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Gruian, F: Robust and Flexible Mapping for Real-time Distributed Applications during the Early Design Phases [p. 935]
Guarnieri, V: FAST-GP: An RTL Functional Verification Framework Based on Fault Simulation on GP-GPUs [p. 562]
Guderian, F: Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Guerra, R: On-line Scheduling of Target Sensitive Periodic Tasks with the Gravitational Task Model [p. 578]
Guilley, S: RSM: A Small and Fast Countermeasure for AES, Secure against First- and Second-order Zero-Offset SCAs [p. 1173]
Guo, X: ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Gupta, A: Runtime Power Estimator Calibration for High-Performance Microprocessors [p. 352]
Gupta, M S: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Gupta, P: VaMV: Variability-aware Memory Virtualization [p. 284]; Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Gupta, R K: Analysis of Instruction-level Vulnerability to Dynamic Voltage and Temperature Variations [p. 1102]
Gupta, S K: Salvaging Chips with Caches beyond Repair [p. 1263]; Layout-Aware Optimization of STT MRAMs [p. 1455]

Haddock, T: Experimentally Driven Verification of Synthetic Biological Circuits [p. 236]
Haedicke, F: A Guiding Coverage Metric for Formal Verification [p. 617]
Hahn, D: Complexity, Quality and Robustness - The Challenges of Tomorrow's Automotive Electronics [p. 870]
Haid, J: Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Hamdioui, S: DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Hameed, F: Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]
Hammami, O: NOCEVE: Network On Chip Emulation and Verification Environment [p. 163]
Hamouche, R: Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Hamouda, A Y: AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Han, K: State-based Full Predication for Low Power Coarse-Grained Reconfigurable Architecture [p. 1367]
Han, X: Out-of-Order Parallel Simulation for ESL Design [p. 141]
Han, Y: A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Hanke, M: Formal Analysis of Sporadic Overload in Real-Time Systems [p. 515]
Hankendi, C: Reducing the Energy Cost of Computing through Efficient Co-Scheduling of Parallel Workloads [p. 994]
Hansen, J: Multi-Token Resource Sharing for Pipelined Asynchronous Systems [p. 1191]
Hansen, R: Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Hapke, F: EDA Solutions to New-Defect Detection in Advanced Process Technologies [p. 123]
Haratsch, E F: Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis [p. 521]
Hardavellas, N: Dynamic Directories: A Mechanism for Reducing On-Chip Interconnect Power in Multicores [p. 479]
Hari, S K S: CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Haron, N Z: DfT Schemes for Resistive Open Defects in RRAMs [p. 799]
Harrant, M: Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Hartmanns, A: State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Hasholzner, R: Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
Hassoun, S: Genetic/Bio Design Automation for (Re-)Engineering Biological Systems [p. 242]
Haubelt, C: Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis [p. 346]
He, Y: Scheduling for Register File Energy Minimization in Explicit Datapath Architectures [p. 388]
Healy, M B: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Hedrich, L: Fast Isomorphism Testing for a Graph-based Analog Circuit Synthesis Framework [p. 757]
Heer, C: Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Hely, D: Evaluation of a New RFID System Performance Monitoring Approach [p. 1439]
Henkel, J: Accurate Source-Level Simulation of Embedded Software with Respect to Compiler Optimizations [p. 382]; Dynamic Cache Management in Multi-Core Architectures through Run-time Adaptation [p. 485]; Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]; Partial Online-Synthesis for Mixed-Grained Reconfigurable Architectures [p. 1555]
Henry, M B: ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Henschel, O P: On ESL Verification of Memory Consistency for System-on-Chip Multiprocessing [p. 9]
Herkersdorf, A: Virtual Platforms: Breaking New Grounds [p. 685]
Hermanns, H: State-of-the-art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems [p. 370]
Heuser, A: Revealing Side-Channel Issues of Complex Circuits by Enhanced Leakage Models [p. 1179]
Ho, T-Y: A Cyberphysical Synthesis Approach for Error Recovery in Digital Microfluidic Biochips [p. 1239]
Holt, J: Verification Coverage of Embedded Multicore Applications [p. 252]
Hopkins, B: SAFER PATH: Security Architecture Using Fragmented Execution and Replication for Protection against Trojaned Hardware [p. 1000]
Howe, R T: Nano-Electro-Mechanical Relays for FPGA Routing: Experimental Demonstration and a Design Technique [p. 1361]
Hsiao, M S: RAG: An Efficient Reliability Analysis of Logic Circuits on Graphics Processing Units [p. 316]; A Scan Pattern Debugger for Partial Scan Industrial Designs [p. 558]
Hsiung, P-A: Congestion-Aware Scheduling for NoC-based Reconfigurable Systems [p. 1561]
Hsu, H-W: On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer [p. 1597]
Hsuing, H: Salvaging Chips with Caches beyond Repair [p. 1263]
Hu, Y: Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, C-Y: A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]; Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, H: Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]; Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Huang, J: Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Huang, K: Off-path Leakage Power Aware Routing for SRAM-based FPGAs [p. 87]
Huang, M: Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Huang, P-K: Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction [p. 1567]
Huang, S: ASIC Implementations of Five SHA-3 Finalists [p. 1006]
Huebner, M: Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems [p. 280]
Huisken, J: Ultra Low Power Litho Friendly Local Assist Circuitry for Variability Resilient 8T SRAM [p. 1042]
Hung, C Y: Challenges in Verifying an Integrated 3D Design [p. 167]
Huss, A: Optimal Energy Management and Recovery for FEV [p. 683]
Huss, S A: Side Channel Analysis of the SHA-3 Finalists [p. 1012]

Ienne, P: Selective Flexibility: Breaking the Rigidity of Datapath Merging [p. 1543]
Ike, A: Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Illikkal, R: PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]
Indaco, M: A Cross-Layer Approach for New Reliability-Performance Trade-Offs in MLC NAND Flash Memories [p. 881]
Irwin, M J: An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Iyengar, V: Challenges in Verifying an Integrated 3D Design [p. 167]
Iyer, R: PCASA: Probabilistic Control-Adjusted Selective Allocation for Shared Caches [p. 473]

Jacobson, H: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
Jafari, F: Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]
Jahn, M: Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jandhyala, V: Moore Meets Maxwell [p. 1275]
Jang, M-W: Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
Jang, S: Mapping into LUT Structures [p. 1579]
Janota, M: QBF-Based Boolean Function Bi-Decomposition [p. 816]
Janssen, R: Large Signal Simulation of Integrated Inductors on Semi-Conducting Substrates [p. 1221]
Jantsch, A: Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling [p. 538]; Parallel Probing: Dynamic and Constant Time Setup Procedure in Circuit Switching NoC [p. 1289]
Jedda, H: Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Jentsch, M: Middleware Services for Network Interoperability in Smart Energy Efficient Buildings [p. 338]
Jeong, K: MAPG: Memory Access Power Gating [p. 1054]
Jerke, G: Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Jha, N K: Enabling Advanced Inference on Sensor Nodes Through Direct Use of Compressively-sensed Signals [p. 437]
Jiang, J: On the Optimality of K Longest Path Generation Algorithm Under Memory Constraints [p. 418]; CrashTest'ing SWAT: Accurate, Gate-Level Evaluation of Symptom-Based Resiliency Solutions [p. 1106]
Jiang, K: Co-Design Techniques for Distributed Real-Time Embedded Systems with Communication Security Constraints [p. 947]
Jiang, L: On Effective TSV Repair for 3D-Stacked ICs [p. 793]; Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Jin, T: Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Jin, Y: Post-Deployment Trust Evaluation in Wireless Cryptographic ICs [p. 965]
Jones, A K: Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]
Jones, D L: Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Jones, S: Optimal Energy Management and Recovery for FEV [p. 683]
Jonsson, F: A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Jouppi, N P.: CACTI-3DD: Architecture-level Modeling for 3D Die-stacked DRAM Main Memory [p. 33]
Jovic, J: Hybrid Simulation for Extensible Processor Cores [p. 288]
Juan, D-C: Statistical Thermal Modeling and Optimization Considering Leakage Power Variations [p. 605]

Kahng, A B: MAPG: Memory Access Power Gating [p. 1054]
Kakoee, M R: A Resilient Architecture for Low Latency Communication in Shared-L1 Processor Clusters [p. 887]
Kalla, P: Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Multipliers [p. 899]
Kalligeros, E: Dynamic-Priority Arbiter and Multiplexer Soft Macros for On-Chip Networks Switches [p. 542]
Kamal, M: An Architecture-Level Approach for Mitigating the Impact of Process Variations on Extensible Processors [p. 467]
Kandemir, M: Performance-Reliability Tradeoff Analysis for Multithreaded Applications [p. 893]
Kang, S: MAPG: Memory Access Power Gating [p. 1054]
Karim, K S: AIR (Aerial Image Retargeting): A Novel Technique for In-Fab Automatic Model-Based Retargeting-for-Yield [p. 1603]
Karimi, N: Test Generation for Clock-Domain Crossing Faults in Integrated Circuits [p. 406]
Karlsson, D: Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Karnik, T: Design for Test and Reliability in Ultimate CMOS [p. 677]
Karri, R: Logic Encryption: A Fault Analysis Perspective [p. 953]
Kasper, M: Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Kathareios, G: A Divide and Conquer Based Distributed Run-time Mapping Methodology for Many-Core Platforms [p. 111]
Katoen, J-P: Model Checking of Scenario-Aware Dataflow with CADP [p. 653]
Katz, Y: Generating Instruction Streams Using Abstract CSP [p. 15]
Kazmierski, T J: Response-surface-based Design Space Exploration and Optimization of Wireless Sensor Nodes with Tunable Energy Harvesters [p. 733]
Keng, B: Non-Solution Implications Using Reverse Domination in a Modern SAT-based Debugging Environment [p. 629]
Kerkhoff, H G: Monitoring Active Filters under Automotive Aging Scenarios with Embedded Instrument [p. 1096]
Kessler, C: Programmability and Performance Portability Aspects of Heterogeneous Multi-/Manycore Systems [p. 1403]
Kestur, S: An FPGA-based Accelerator for Cortical Object Classification [p. 691]
Khatri, S P: A Fast, Source-Synchronous Ring-based Network-on-Chip Design [p. 1489]
Khellah, M: Design for Test and Reliability in Ultimate CMOS [p. 677]
Kiamehr, S: NBTI Mitigation by Optimized NOP Assignment and Insertion [p. 218]
Kim, D: A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]
Kim, H: On-Chip Source Synchronous Interface Timing Test Scheme with Calibration [p. 1146]
Kim, N S: Workload-Aware Voltage Regulator Optimization for Power Efficient Multi-Core Processors [p. 1134]
Kim, Y: Multiple-Source and Multiple-Destination Charge Migration in Hybrid Electrical Energy Storage Systems [p. 169]; A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]; Embedded Systems and Software Challenges in Electric Vehicles [p. 424]
Kirsch, C: Cyber-Physical Cloud Computing: The Binding and Migration Problem [p. 1425]
Kluge, F: Time Analysable Synchronisation Techniques for Parallelised Hard Real-Time Applications [p. 671]
Knoedler, K: Optimal Energy Management and Recovery for FEV [p. 683]
Knoll, A: Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
Knoth, C: Current Source Modeling for Power and Timing Analysis at Different Supply Voltages [p. 923]
Kocabas, U: PUF-based Secure Test Wrapper Design for Cryptographic SoC Testing [p. 866]
Kocik, R: Component-Based and Aspect-Oriented Methodology and Tool for Real-Time Embedded Control Systems Design [p. 1421]
Koenig, R: A Cycle-Approximate, Mixed-ISA Simulator for the KAHRISMA Architecture [p. 21]
Kogel, T: Virtual Platforms: Breaking New Grounds [p. 685]
Kondratyev, A: Exploiting Area/Delay Tradeoffs in High-Level Synthesis [p. 1024]
Kotiyal, S: Mach-Zehnder Interferometer Based Design of All Optical Reversible Binary Adder [p. 721]
Kouters, T: Memory-Map Selection for Firm Real-Time SDRAM Controllers [p. 828]
Kress, R: Panel: What Is EDA Doing for Trailing Edge Technologies? [p. 874]
Kriebel, F: Power-Efficient Error-Resiliency for H.264/AVC Context-Adaptive Variable Length Coding [p. 697]
Krinke, A: Hierarchical Propagation of Geometric Constraints for Full-Custom Physical Design of ICs [p. 1471]
Kristic, M: Exploring Pausible Clocking Based GALS Design for 40-nm System Integration [p. 1118]
Krone, S: Towards A Wireless Medic Smart Card - Invited Paper [p. 1483]
Kulkarni, J: Design for Test and Reliability in Ultimate CMOS [p. 677]
Kuntz, S: Timing Modeling with AUTOSAR - Current State and Future Directions [p. 805]
Kunze, M: Measuring and Improving the Robustness of Automotive Smart Power Microelectronics [p. 872]
Kural, E: Optimal Energy Management and Recovery for FEV [p. 683]
Kuwamura, S: Fast Cycle Estimation Methodology for Instruction-Level Emulator [p. 248]
Kwon, S: A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem [p. 264]

Lafaye, M: Model Driven Resource Usage Simulation for Critical Embedded Systems [p. 312]
Lai, L-C: Design and Analysis of Via-Configurable Routing Fabrics for Structured ASICs [p. 1479]
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Landis, D L: Hazard Driven Test Generation for SMT Processors [p. 256]
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Raabe, A: Static Scheduling of a Time-Triggered Network-on-Chip Based on SMT Solving [p. 509]; Bounding WCET of Applications Using SDRAM with Priority Based Budget Scheduling in MPSoCs [p. 665]
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Reinman, G: Dynamically Reconfigurable Hybrid Cache: An Energy-Efficient Last-Level Cache Design [p. 45]
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Rivers, J A: Power Management of Multi-Core Chips: Challenges and Pitfalls [p. 977]
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Weiss, R: Estimation Based Power and Supply Voltage Management for Future RF-Powered Multi-Core Smart Cards [p. 358]
Wenger, M: Batteries and Battery Management Systems for Electric Vehicles [p. 971]
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Whitty, S: A High-Performance Dense Block Matching Solution for Automotive 6D-Vision [p. 268]
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Wille, R: Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis [p. 1036]; Debugging of Inconsistent UML/OCL Models [p. 1078]; Eliminating Invariants in UML/OCL Models [p. 1142]
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Wong, W-F: Extending the Lifetime of NAND Flash Memory by Salvaging Bad Blocks [p. 260]
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Wu, W: Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]
Wu, Y-L: Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]

Xhakoni, A: Impact of TSV Area on the Dynamic Range and Frame Rate Performance of 3D-Integrated Image Sensors [p. 836]
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Xie, Z: Energy-Efficient Branch Prediction with Compiler-Guided History Stack [p. 449]
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Yakoushkin, S: Hybrid Simulation for Extensible Processor Cores [p. 288]
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Yang, J: Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
Yang, S: Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Yang, X: Almost Every Wire is Removable: A Modeling and Solution for Removing Any Circuit Wire [p. 1573]
Yang, Y: Playing Games with Scenario- and Resource-Aware SDF Graphs Through Policy Iteration [p. 194]
Yang, Y-C: A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis [p. 147]
Yang, Y-S: Leveraging Reconfigurability to Raise Productivity in FPGA Functional Debug [p. 292]
Ye, R: Clock Skew Scheduling for Timing Speculation [p. 929]
Ye, Z: Weighted Area Technique for Electromechanically Enabled Logic Computation with Cantilever-Based NEMS Switches [p. 727]
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Yu, W: Efficient Variation-Aware EM-Semiconductor Coupled Solver for the TSV Structures in 3D IC [p. 1409]
Yu, Z: A Complexity Adaptive Channel Estimator for Low Power [p. 1531]
Yuan, F: Clock Skew Scheduling for Timing Speculation [p. 929]
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Zeng, H: Task Implementation of Synchronous Finite State Machines [p. 206]
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Zhang, C: Fair Energy Resource Allocation by Minority Game Algorithm for Smart Buildings [p. 63]; Voltage Propagation Method for 3-D Power Grid Analysis [p. 844]; Spintronic Memristor Based Temperature Sensor Design with CMOS Current Reference [p. 1301]
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Zhang, L: A Clustering-Based Scheme for Concurrent Trace in Debugging NoC-Based Multicore Systems [p. 27]
Zhang, P: Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Zhang, Y: Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]; Asymmetry of MTJ Switching and Its Implication to STT-RAM Designs [p. 1313]; Architecting a Common-Source-Line Array for Bipolar Non-Volatile Memory Devices [p. 1451]
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Zhao, S: Real-time Implementation and Performance Optimization of 3D Sound Localization on GPUs [p. 832]
Zheng, C: Low Power Aging-Aware Register File Design by Duty Cycle Balancing [p. 546]
Zheng, L-R: A Multi-Parameter Bio-Electric ASIC Sensor with Integrated 2-Wire Data Transmission Protocol for Wearable Healthcare System [p. 443]
Zheng, Y: Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication [p. 1501]
Zhou, H: Clock Skew Scheduling for Timing Speculation [p. 929]
Zimmermann, J: Optimal Energy Management and Recovery for FEV [p. 683]; Analysis of Multi-Domain Scenarios for Optimized Dynamic Power Management Strategies [p. 862]
Ziv, A: Generating Instruction Streams Using Abstract CSP [p. 15]; Approximating Checkers for Simulation Acceleration [p. 153]
Zjajo, A: Transistor-Level Gate Model Based Statistical Timing Analysis Considering Correlations [p. 917]
Zohner, M: Side Channel Analysis of the SHA-3 Finalists [p. 1012]
Zorian, Y: Design for Test and Reliability in Ultimate CMOS [p. 677]
Zou, Q: 3DHLS: Incorporating High-Level Synthesis in Physical Planning of Three-Dimensional (3D) ICs [p. 1185]
Zou, Y: Combining Module Selection and Replication for Throughput-Driven Streaming Programs [p. 1018]
Zuluaga, M: Predicting Best Design Trade-offs: A Case Study in Processor Customization [p. 1030]
Zyulkyarov, F: TagTM - Accelerating STMs with Hardware Tags for Fast Meta-Data Access [p. 39]