7.3 Hot Topic - Advances in Hardware Trojans Detection
Date: Wednesday 11 March 2015
Time: 14:30 - 16:00
Location / Room: Stendhal
Organiser:
Julien Francq, Airbus Defence & Space CyberSecurity, FR
Chair:
Giorgio Di Natale, LIRMM, CNRS/University of Montpellier, FR
Hardware Trojans (HTs) are malicious modifications of an Integrated Circuit (IC) during its design flow. These added transistors could induce in the infected IC some malicious effects. Complete trust in ICs has been now lost because of the outsourcing of the fabrication of the ICs and the complexity of the IC design flow. This special session will present some advances in HT detection developed in French funded research project HOMERE.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 14:30 | 7.3.1 | INTRODUCTION TO HARDWARE TROJAN DETECTION METHODS Speakers: Julien Francq1 and Florian Frick2 1Cassidian, FR; 2University of Stuttgart, DE Abstract Hardware Trojans (HTs) are identified as an emerging threat for the integrity of Integrated Circuits (ICs) and their applications. Attackers attempt to maliciously manipulate the functionality of ICs by inserting HTs, potentially causing disastrous effects (Denial of Service, sensitive information leakage, etc.). Over the last 10 years, various methods have been proposed in literature to circumvent HTs. This article introduces the general context of HTs and summarizes the recent advances in HT detection from a French funded research project named HOMERE. Some of these results will be detailed in the related special session. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 14:45 | 7.3.2 | NEW TESTING PROCEDURE FOR FINDING INSERTION SITES OF STEALTHY HARDWARE TROJANS Speakers: Sophie Dupuis, Papa-Sidy Ba, Marie-Lise Flottes, Giorgio Di Natale and Bruno Rouzeyre, LIRMM, FR Abstract Hardware Trojans (HTs) are malicious alterations to a circuit. These modifications can be inserted either during the design phase or during the fabrication process. Due to the diversity of Hardware Trojans, detecting and/or locating them are challenging tasks. Numerous approaches have been proposed to address this problem. Methods based on logic testing consist in trying to activate potential HTs and detect erroneous outputs during test. However, HTs are stealthy in nature i.e. mostly inactive unless they are triggered by a very rare condition. The activation of a HT is therefore a major challenge. In this paper, we propose a new testing procedure dedicated to identifying where a possible HT may be easily inserted and generating the test patterns that are able to excite these sites. The selection of the sites is based on the assumption that the HT (i) is triggered by signals with low controllability, (ii) combines them using gates in close proximity in the circuit's layout, and (iii) without introducing new gates in critical paths. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:00 | 7.3.3 | HARDWARE TROJAN DETECTION BY DELAY AND ELECTROMAGNETIC MEASUREMENTS Speakers: X-T. Ngo1, I Exurville2, S Bhasin1, Jean-Luc Danger1, Sylvain Guilley1, Z Najm1, Jean Baptiste Rigaud3 and Bruno Robisson2 1Télécom ParisTech, FR; 2CEA, FR; 3EMSE, FR Abstract Hardware trojan (HT) inserted in integrated circuits have received special attention of researchers. In this paper, we present firstly a novel HT detection technique based on path delays measurements. A delay model is established for a net, which consider intra-die process variations. Secondly, we show how to detect HT using ElectroMagnetic (EM) measurements. We study the HT detection probability according to its size taking into account the inter-die process variations with a set of FPGAs. The results show that: there is a probability superior than 95% with a false negative rate of 5% to detect a HT bigger than 1.7% of the original circuit. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 15:30 | 7.3.4 | A HIGH EFFICIENCY HARDWARE TROJAN DETECTION TECHNIQUE BASED ON FAST SEM IMAGING Speakers: Franck Courbon1, Philippe Loubet-Moundi2, Fournier Jacques3 and Assia Tria3 1GEMALTO Security Labs/Ecole des Mines de Saint-Etienne, FR; 2Gemalto, FR; 3CEA Tech Region DPACA/LSAS, FR Abstract In the semiconductor market where more and more companies become fabless, malicious integrated circuits' modifications are seen as possible threats. Those Hardware Trojans can have various effects and can be implemented by different entities with different means. This article includes the integration of an almost automatic Hardware Trojan detection. The latter is based on a visual inspection implemented within the integrated circuit life cycle. The proposed detection methodology is quite efficient regarding tools, user experience and time needed. A single layer of the chip is accessed and then imaged with a Scanning Electron Microscope (SEM). The acquisition of several hundred images at high magnification is automated as does the images registration. Then depending on the reference availability, one can check if any supplementary gates have been inserted in the design using a golden reference or a graphic/text design file. Depending on the reference, either basic image processing is used to compare the chip extracted image with a golden model or some pattern recognition can be used to retrieve the number of occurrences of each standard cell. The depicted methodology aims to detect any gate modification, substitution, removal or addition and so far require an invasive approach and a reference. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 16:00 | End of session Coffee Break in Exhibition Area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |
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