W05 3D Integration Technology, Architecture, Design, Package, Automation, and Test

Printer-friendly versionPDF version


08:15W05.1SESSION 1: OPENING and 1st Keynote

Pascal VIVET, CEA-Leti, FR

08:15W05.1.1Welcome Address
Pascal VIVET, CEA-Leti, FR

08:20W05.1.2Keynote: "Computing in 3D"
Paul Franzon, North Carolina State University, US


3DIC technology refers to stacking and interconnecting chips and substrates ("interposers") with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. At NCSU, we have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Main memory redesign, using both DRAM and RRAM, is explored to show potential for an order of magnitude reduction. Possible extensions to Cortical Processing are discussed.


Paul D. Franzon is currently a Distinguished Alumni Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.

09:00W05.2Special Session: "3D Memories"

Christian Weis, Microelectronic System Research Group, DE

What are current 3D memory technologies offering? This special session will put a spot on TSV stacking for high bandwidth memories, the influence of 3D memory on computing and real facts about 3D memories.  

09:00W05.2.1TSV stacking design and packaging for high bandwidth memories with 1GHz sampling digitized noize monitor
Kazuki Fukuoka, Renesas Electronics, JP

09:20W05.2.2How 3D Memory is Changing Computing
Robert Patti, Tezzaron Semiconductor, US

09:40W05.2.33D Memories: Facts and Fiction
Andreas Hansson, ARM Ltd, GB

10:00W05.2.4Poster Session and Coffee Break

For the list of posters see below.

10:30W05.3SESSION 2: Invited Talk and Panel

Françoise von Trapp, 3D InCites, US

Krishnendu Chakrabarty, Duke University, US
Brendan Farley1, Denis Dutoit2, Hsien-Hsin S. Lee3, Geert Van der Plas4 and Mustafa Badaroglu5

It's official. Memory has moved into the interposer and 3D stacked IC space with many companies announcing stacked Memory products for high-end computing applications including networking, data servers, and gaming.  But does this solve the memory bandwidth issue across the board? Will we see similar memory stacks in consumer products? And if so, what has to happen? What requirements transpire for TSV-based interconnects and interposers? This provocative panel (with interactive audience participation!) will offer perspectives from R&D, manufacturing, and end-users.

13:00W05.4Special Session: "Die-package co-design benefits and challenges"

Herb Reiter, EDA2ASIC, US

Interposer and 3D-IC designs pack more functionality into a smaller space (cm3). While saving total power dissipation (in Watts) they significantly increase power density (in Watts/cm3). To keep the junction temperatures of the closely packed dies within limits and guarantee functionality, parametrics and reliability, all at an acceptable unit cost, the IC package and its components play a major role. Only by considering the package characteristics already during the IC design process, an optimal solution can be found. Close cooperation between EDA tools developers, IC designers and IC manufacturers is required to develop and agree upon a user friendly and cost-effective die-package co-design environment. The presenters will detail the current challenges and outline key benefits of an emerging die-package co-design methodology.  

After this special session, there is time for 10 minutes wrap-up and discussion.

13:00W05.4.1The 3D-IC EcoSystem today and how to strengthen it further
Herb Reiter, EDA2ASIC, US

13:20W05.4.2Data Handling for Chip-Package-Board Co-Design and Design Rule Check
Andy Heinig, Fraunhofer IIS/EAS, DE

13:40W05.4.3Silicon-Package Co-Design Challenges from 2D to 3D
Georg Kimmich, STMicrolectronics, FR

14:00W05.4.4IC design aspects of die-package co-design
John Ferguson, Mentor Graphics Corp, US

14:30W05.4.5Poster Session and Coffee Break

For the list of posters see below.

15:00W05.5SESSION 3: Test and Technology Challenges for 3D ICs

Makoto Nagata, Kobe University, JP

15:00W05.5.1Impact of Multi-Vt technique in Eliminating Thermal Runaway during Testing of 3D chips
Seetal Potluri1, Satya Trinadh Adireddy2, S. G. Singh2, Sobhan Babu Ch.2 and Kamakoti Veezhinathan1
1IIT Madras, IN; 2IIT Hyderabad, IN

15:18W05.5.23D-IC Session-based vs Session-less Test Scheduling: a case study
Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale and Bruno Rouzeyre, LIRMM, FR

15:36W05.5.33D IC Test through Low Noise Power Line Methodology
Alberto Pagani and Allessandro Motta, STMicroelectronics, IT

15:54W05.5.4Broadband Metal-Insulator-Metal Capacitors on Silicon Interposer for Low Impedance Power Distribution Network
Nao Ueda1, Cesar Roda Neve2, Mikael Detalle2, Eric Beyne2, Geert Van der Plas2 and Makoto Nagata1
1Kobe University, JP; 2IMEC, BE

16:12W05.5.5A TSV to TSV, A TSV to Metal Interconnects, and A TSV to Active Device Coupling Capacitance: Analysis and Recommendations
Khaled Mohamed, Mentor, EG

16:28W05.6Poster List
16:28W05.6.1A New Contactless Substrate Shipper for ultrathin, 3D, lensed or bumbed Wafers
Jorgen Lundgren, Entegris GmbH, DE

16:28W05.6.2Test and reconfiguration of TSV defect in 3D-IC
Mohamed Benabdeladhim, Dept. of Physics, Faculty of Science of Monastir, TN

16:28W05.6.3MEMS Sensor and IC Developement: Innovative Tools, Methods, Design Practive
Grzegorz Janczyk and Tomasz Bieniek, ITE Warsaw, PL

16:28W05.6.4Pathfinding for 3D Designs Based on Interposer
Vladimir Pasca1, Claudia Rusu1, Meycène Toumi2 and Pascal VIVET3
1Atrenta, Grenoble, FR; 2CEA Leti, FR; 3CEA-Leti, FR

16:28W05.6.5Modeling of Rentention Time Errors of 3D-stacked DRAMs based on Real Chip Measurements
Christian Weis1, Matthias Jung2, Pascal VIVET3, Cristiano Santos4 and Norbert Wehn2
1Microelectronic System Research Group, DE; 2University of Kaiserslautern, DE; 3CEA-Leti, FR; 4CEA-Leti, Grenoble and UFRGS, Porto Alegre, Brazil, FR