W05 3D Integration Technology, Architecture, Design, Package, Automation, and Test

Chair:
Pascal VIVET, CEA-Leti, FR

Abstract:

3DIC technology refers to stacking and interconnecting chips and substrates ("interposers") with Through Silicon Vias (TSVs). Industry is gearing up for widespread introduction of this technology with the 22 nm node. At NCSU, we have been pursuing a range of approaches to enable low power computing. As well as 3DIC these include heterogeneous computing, powered optimized SIMD units, optimized memory hierarchies, and MPI with post-silicon customized interconnect. Heterogeneous computing refers to the concept of building a mix of CPUs and memories that in turn enable in-situ tuning of the compute load to the compute resources. We introduce the concept of Fast Thread Migration using 3DIC technologies. We present the design of a power optimized SIMD unit in which over half of the power is employed in the FP units. A parallel computer is built using an MPI paradigm. Codes are analyzed so that the MPI interconnect can be power optimized post-silicon. Emerging 3D memories have potential to be employed as Level 2 and Level 3 caches, and this is explored using the Tezzaron 3D memory. As scaling and power optimization occurs, the main memory increasingly dominates the power consumption. Main memory redesign, using both DRAM and RRAM, is explored to show potential for an order of magnitude reduction. Possible extensions to Cortical Processing are discussed.

Bio:

Paul D. Franzon is currently a Distinguished Alumni Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and three companies he cofounded, Communica, LightSpin Technologies and Polymer Braille Inc. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 300 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, received the Alcoa Research Award in 2005, and the Board of Governors Teaching Award in 2014. He served with the Australian Army Reserve for 13 years as an Infantry Solider and Officer. He is a Fellow of the IEEE.

Chair:
Christian Weis, Microelectronic System Research Group, DE

What are current 3D memory technologies offering? This special session will put a spot on TSV stacking for high bandwidth memories, the influence of 3D memory on computing and real facts about 3D memories.  

For the list of posters see below.

Moderator:
Françoise von Trapp, 3D InCites, US

It's official. Memory has moved into the interposer and 3D stacked IC space with many companies announcing stacked Memory products for high-end computing applications including networking, data servers, and gaming.  But does this solve the memory bandwidth issue across the board? Will we see similar memory stacks in consumer products? And if so, what has to happen? What requirements transpire for TSV-based interconnects and interposers? This provocative panel (with interactive audience participation!) will offer perspectives from R&D, manufacturing, and end-users.

Chair:
Herb Reiter, EDA2ASIC, US

Interposer and 3D-IC designs pack more functionality into a smaller space (cm3). While saving total power dissipation (in Watts) they significantly increase power density (in Watts/cm3). To keep the junction temperatures of the closely packed dies within limits and guarantee functionality, parametrics and reliability, all at an acceptable unit cost, the IC package and its components play a major role. Only by considering the package characteristics already during the IC design process, an optimal solution can be found. Close cooperation between EDA tools developers, IC designers and IC manufacturers is required to develop and agree upon a user friendly and cost-effective die-package co-design environment. The presenters will detail the current challenges and outline key benefits of an emerging die-package co-design methodology.  

After this special session, there is time for 10 minutes wrap-up and discussion.

For the list of posters see below.

Chair:
Makoto Nagata, Kobe University, JP