9.7 Test Generation, Fault Simulation and Diagnosis
Date: Thursday 12 March 2015
Time: 08:30 - 10:00
Location / Room: Les Bans
Chair:
Jacob Abraham, The University of Texas at Austin, US
Co-Chair:
Bernd Becker, University Freiburg, DE
Speeding-up the test process is crucial from a technical and economical point of view. Novel methods are presented to accelerate silicon debug, fault simulation, test generation and diagnosis.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.7.1 | QUICK ERROR DETECTION TESTS WITH FAST RUNTIMES FOR EFFECTIVE POST-SILICON VALIDATION AND DEBUG Speakers: David Lin1, Eswaran S2, Sharad Kumar2, Eric Rentschler3 and Subhasish Mitra1 1Stanford University, US; 2Freescale Semiconductor, IN; 3Advanced Micro Devices, US Abstract Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED). Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.7.2 | (Best Paper Award Candidate) GPU-ACCELERATED SMALL DELAY FAULT SIMULATION Speakers: Eric Schneider1, Stefan Holst2, Michael Kochte1, Xiaoqing Wen2 and Hans-Joachim Wunderlich1 1University of Stuttgart, DE; 2Kyushu Institute of Technology, JP Abstract The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multi-million gate designs without fault dropping for the first time. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.7.3 | FAULT SIMULATION WITH PARALLEL EXACT CRITICAL PATH TRACING IN MULTIPLE CORE ENVIRONMENT Speakers: Maksim Gorev, Raimund Ubar and Sergei Devadze, Tallinn University of Technology, EE Abstract A novel fault simulation method is proposed, based on exact critical path tracing beyond the Fan-out-Free Regions (FFR) throughout the fully simulated circuit. The method exploits two types of parallelism: bit-level parallelism for multiple pattern reasoning, and distribution the fault reasoning process between different cores in a multi-core processor environment. To increase the speed and accuracy of fault simulation, compared with previous methods, a mixed level fault reasoning approach is developed, were the fan-out re-convergence is handled on the higher FFR network level, and the fault simulation inside of FFRs relies on the gate-level information. To allow a uniform and seamless fault reasoning, Structurally Synthesized BDDs (SSBDD) are used for modeling on both levels. Experimental research demonstrated very promising results in increasing the speed and scalability of the method. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:45 | 9.7.4 | ON THE AUTOMATIC GENERATION OF SBST TEST PROGRAMS FOR IN-FIELD TEST Speakers: Andreas Riefert1, Riccardo Cantoro2, Matthias Sauer1, Matteo Sonza Reorda2 and Bernd Becker1 1University of Freiburg, DE; 2Politecnico di Torino, IT Abstract Software-based self-test (SBST) techniques are used to test processors against permanent faults introduced by the manufacturing process (often as a complementary approach with respect to DfT) or to perform in-field test in safety-critical applications. A major obstacle to their adoption is the high cost for developing effective test programs, since there is still a lack of suitable EDA algorithms and tools able to automatically generate SBST test programs. An efficient ATPG algorithm can serve as the foundation for the automatic generation of SBST test programs. In this work we first highlight the additional constraints characterizing SBST test programs wrt functional ones, with special emphasis on their usage for in-field test; then, we describe an ATPG framework targeting stuck-at faults based on Bounded Model Checking. The framework allows the user to flexibly specify the requirements of SBST test programs in the considered scenario. Finally, we demonstrate how a set of properly chosen requirements can be used to generate test programs matching these constraints. In our experiments we evaluate the framework with the miniMIPS microprocessor. The results show that the proposed method is the first able to automatically generate SBST test programs whose fault efficiency is superior to those produced with state-of-the-art manual approaches. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-18, 1031 | EXPLORING THE IMPACT OF FUNCTIONAL TEST PROGRAMS RE-USED FOR POWER-AWARE TESTING Speakers: Aymen Touati1, Alberto Bosio2, Luigi Dilillo2, Patrick Girard2, Arnaud Virazel2, Paolo Bernardi3 and Mateo Sonza Reorda3 1LIRMM, FR; 2LIRMM-UM2/CNRS, FR; 3Politecnico di Torino, IT Abstract Abstract— High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget. Keywords—Power Aware Test; Functional and Structural test; microprocessor test; ATPG. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP4-19, 621 | A BREAKPOINT-BASED SILICON DEBUG TECHNIQUE WITH CYCLE-GRANULARITY FOR HANDSHAKE-BASED SOC Speakers: Hsin-Chen Chen1, Chen-Rong Wu1, Katherine Shu-Min Li2 and Kuen-Jon Lee1 1National Cheng Kung University, TW; 2National Sun Yat-sen University, TW Abstract The breakpoint-based silicon debug approach allows users to stop the normal (system) operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume the normal operations for further debugging. However, most previous work on this approach adopts the transaction-level or handshake-level of granularity, i.e., the CUDs can be stopped only when a transaction or a handshake operation is completed. The granulations at these levels are often too coarse when a transaction or a handshake operation requires a large number of cycles to complete. In this paper, we present a novel debug mechanism, called the Protocol Agency Mechanism (PAM), which allows the breakpoint-based debug technique to be applied at the cycle- level granularity. The PAM can deal with transaction invalidation as well as protocol violation that may occur when a system is stopped and resumed. Experimental results show that the area overhead of the PAM is quite small and the performance impact on the system is negligible. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:02 | IP4-20, 602 | FAULT DIAGNOSIS IN DESIGNS WITH EXTREME LOW PIN TEST DATA COMPRESSORS Speakers: Subhadip Kundu1, Parthajit Bhattacharya1 and Rohit Kapur2 1Synopsys India, IN; 2Synopsys Inc., US Abstract Diagnosis plays an important role to ramp up yield during IC manufacturing process. Limited observability due to test response compaction negatively affects the diagnosis procedure. With modern compressors - targeting very high test data compression, diagnosis becomes even more complicated. In this paper, a complete diagnosis methodology focussing on a novel mapping algorithm has been described. The mapping algorithm maps failures from compressor pins to scan cells with great accuracy (even in presence of don't cares in the responses), so that, normal scan diagnosis can be used to find out the actual defects. Experimental results on different industrial designs have proved that the proposed method almost match scan based diagnosis results. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:03 | IP4-21, 573 | OPTIMIZING DYNAMIC TRACE SIGNAL SELECTION USING MACHINE LEARNING AND LINEAR PROGRAMMING Speakers: Charlie Shucheng Zhu and Sharad Malik, Princeton University, US Abstract The success of post-silicon validation is limited by the low observability of the signals on the chip under debug. Trace buffers are used to enhance visibility of a subset of the internal signals during the chip's operation. These trace signals can be selected statically, i.e. the same trace signals are used through an entire debugging run, or dynamically where a different set of signals can be used in different parts of a debugging run. The focus of this work is on dynamic trace signal selection. Our technique uses machine learning for classification of different groups of inputs that are likely to trigger different faults, and a linear programming based optimization method for selecting the different sets of trace signals for different combinations of inputs and states. In contrast to existing methods, this technique is applicable to both transient and permanent faults. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |
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