Date: Tuesday 10 March 2015
Time: 17:00 - 18:30
Location / Room: Meije

Chair:
Dan Alexandescu, iRoC, FR

Co-Chair:
Emmanuel Simeu, TIMA, FR

This session introduces test and validation industrial experiments. Each experiment addresses the challenges of system validation and test and shows lessons learned from industry

Time	Label	Presentation Title Authors
17:00	4.5.1	SYSTEMATIC APPLICATION OF THE ISO 26262 ON A SEOOC SUPPORT BY APPLYING A SYSTEMATIC REUSE APPROACH Speakers: Alejandra Ruiz1, Alberto Melzi2 and Tim Kelly3 1TECNALIA, ES; 2Centro Ricerche FIAT, IT; 3University of York, GB Abstract Automotive domain is suffering a huge transformation on the sector. The full electric vehicle is playing a role in updating the electronic systems on the car. The Electric parking system is one of those systems that are being evolving. On the other hand the entrance of the ISO 26262 [1] functional safety standard has impacted on the automotive designs. The ISO 26262 does include The Safety Element out of Context (SEooC) on the standard. However it does not mention how to follow a systematic process in order to apply the SEooC. On this paper we present our experience on the application of the SEooC concept from the ISO 26262 to an Electric parking system. We have followed a systematic approach that takes into account the needs for a safe reuse of the elements into the whole vehicle. Download Paper (PDF; Only available from the DATE venue WiFi)
17:15	4.5.2	TIMING ANALYSIS OF AN AVIONICS CASE STUDY ON COMPLEX HARDWARE/SOFTWARE PLATFORMS Speakers: Franck Wartel1, Leonidas Kosmidis2, Adriana Gogonel3, Andrea Baldovin4, Zoe Stephenson5, Benoit Triquet1, Eduardo Quinones6, Code Lo3, Enrico Mezzetti7, Ian Broster5, Jaume Abella8, Liliana Cucu-Grosjean3, Tullio Vardanega4 and Francisco Cazorla9 1Airbus, FR; 2Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 3INRIA, FR; 4University of Padova, IT; 5Rapita Systems, Ltd., GB; 6Barcelona Supercomputing Center, ES; 7University of Padua, IT; 8Barcelona Supercomputing Center (BSC-CNS), ES; 9Barcelona Supercomputing Center and IIIA-CSIC, ES Abstract Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular have been shown to facilitate the estimation of the worst-case execution time (WCET). MBPTA relies on specific hardware and software support to randomise and/or upper bound a number of sources of execution time variation to drastically reduce the need for user-provided information, thus replacing uncertainty by probabilities. MBPTA has been shown effective in real case studies for specific single-core processor designs. However, some other hardware features and the advent of multicores challenge MBPTA application in industrial-size programs. While solutions to those challenges have been proven on benchmarks, they have not been proven yet on real-world applications, whose timing analysis is far more challenging than that of simple benchmarks. This paper discusses the application of MBPTA to a real avionics system in the context of (1) software-only single-core solutions and (2) hardware-only multicore solutions with an ARINC 653 operating system. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	4.5.3	SILICON PROOF OF THE INTELLIGENT ANALOG IP DESIGN FLOW FOR FLEXIBLE AUTOMOTIVE COMPONENTS Speakers: Torsten Reich, H. D. Benjamin Prautsch, Uwe Eichler and René Buhl, Fraunhofer Institute for Integrated Circuits IIS, Design Automation Division EAS, DE Abstract In this brief paper we present the successful silicon validation of the Intelligent Analog IP (IIP) design flow applied to the design of a SMART sensor IC for automotive requirements. Using a library of reconfigurable and robust analog IP we fast create parameterized cells up to high complexity levels including the corresponding layouts. This allows us (1) to overcome time-consuming handcrafted analog re-design cycles, (2) to include the effects of layout parasitics into the optimization loop, and thus (3) to fast achieve different specifications even for multiple technologies. We show that the IIP design flow leads to a strong improvement of design efficiency, silicon performance, and yield. Download Paper (PDF; Only available from the DATE venue WiFi)
17:45	4.5.4	FAST OPTICAL SIMULATION FROM A REDUCED SET OF IMPULSE RESPONSES USING SYSTEMC AMS Speakers: Fabien Teysseyre1, David Navarro1, Ian O'Connor1, Francesco Cascio2, Fabio Cenni2 and Olivier Guillaume2 1École Centrale de Lyon, FR; 2STMicroelectronic, FR Abstract In this paper we propose a methodology to simulate the optical filtering system of a camera module with limited access to proprietary data. The target of the simulation is the virtual prototyping of the overall camera module for a fine tuning of the auto-focus mechanism. For the optical system modeling, the methodology is based on the usage of some point spread functions (PSFs). The use of the full set of PSFs is computationally costly and memory space consuming hence compromising the usability of the optical model in the full system virtual prototyping. To improve the model execution time, PSFs interpolation and free-space propagation techniques are used: they allow reducing the sampling space with minimal impact on the accuracy of the model (sharpness error less than 2%). The total speed-up gain with respect to the standard non-optimized model is provided by two contributors. First, the interpolation technique leads to a speed-up linked to the PSFs number reduction. Second, the caching of computationally intense processes enables speed-up scaling with the number of frames. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	4.5.5	DESIGNER-LEVEL VERIFICATION -- AN INDUSTRIAL EXPERIENCE STORY Speakers: Stephen Bergman1, Gabor Bobok1, Walter Kowalski1, Shlomit Koyfman2, Shiri Moran2, Ziv Nevo2, Avigail Orni2, Viresh Paruthi1, Wolfgang Roesner1, Gil Shurek2 and Vasantha Vuyyuru1 1IBM, US; 2IBM, IL Abstract Designer-level verification (DLV) is now widely accepted as a necessary practice in the hardware industry. More than ever, logic designers are held responsible for the initial validation of modules they develop, before these are released to systematic verification. DLV requires specific tools and methods adapted for designers, who are not full-time verification experts. We present user experience stories and usage statistics, describing how DLV has been practiced in our company, using a dedicated tool developed for this purpose. A typical pattern that emerges is of designers devoting short, fragmented time periods to DLV work, interleaved with other logic development tasks. We observe that the deployed DLV tool supports this mode of work, since it is simple and intuitive. This demonstrates that a suitable tool can help DLV become an integral part of a logic design project. Download Paper (PDF; Only available from the DATE venue WiFi)
18:15	4.5.6	MINIMUM CURRENT CONSUMPTION TRANSITION TIME OPTIMIZATION METHODOLOGY FOR LOW POWER CTS Speaker: Vibhu Sharma, NXP Research, NL Abstract The clock tree network can consume up to 40% of the power budget and is one of the limiting factors for realizing low power designs. This paper presents a novel clock transition time optimization based low power clock tree synthesis, for the non-throughput constraint designs. The proposed methodology quantifies the dependence of short circuit and switching power of the buffers on the input clock transition time, with the newly defined "weighted current strength" parameter. The reduction in the weighted current strength parameter value directly maps into the reduction in the total dynamic power of the clock tree. The proposed methodology determines the transition time constraint values for the clock signals which result in the minimum weighted current strength for the synthesized clock tree network. This technique results in up to 34% reduction in the dynamic power of the clock tree network with the existing clock tree synthesis tools and the clock tree library. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session