Date: Thursday 27 March 2014
Time: 14:30 - 16:30
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB11.01	CYCLOSE: DESIGNING CLOUD-BASED SELF-HEALING CYBER-PHYSICAL SYSTEMS Authors: Giulio Gambardella1, Silviu Folea2, Mihai Hulea2, Liviu Miclea2, George Mois2, Teodora Sanislav2, Marco Indaco1, Paolo Prinetto1, Daniele Rolfo1 and Pascal Trotta1 1Politecnico di Torino, IT; 2Universitatea Tehnica din Cluj-Napoca Departamentul de Automatica, RO Abstract Cyber-Physical Systems (CPSs) are a new generation of systems capable to represent more than networking and information technology, information and knowledge being integrated into physical objects. These type of systems are physical and engineered systems whose actions are monitored, controlled, and integrated by a computing and communication kernel. The Cyclose project aims at developing: (1) an infrastructure for designing self-healing Cyber-Physical Systems (CPSs) using cloud computing technology; (2) an experimental model for CPSs using wireless sensor networks (WSNs) for data acquisition, reliable hardware components based on reconfigurable devices - Field Programmable Gate Arrays (FPGAs) and cloud computing technology to store, manage and analyse data in a large context. More information ...
UB11.02	BRIDGING MATLAB/SIMULINK AND ESL DESIGN VIA AUTOMATIC CODE GENERATION Authors: Liyuan Zhang, Michael Glaß and Jürgen Teich, University of Erlangen-Nuremberg, DE Abstract Matlab/Simulink is today's de-facto standard for model-based design in domains such as control engineering and signal processing. Commercial tools are available to generate embedded C or HDL code directly from a Simulink model. However, Simulink models are purely functional models and, hence, designers cannot seamlessly consider the architecture that a Simulink model is later implemented on. In particular, it is not possible to explore the different architectural alternatives and investigate the arising interactions and side-effects directly within Simulink. To benefit from Matlab/Simulink's algorithm exploration capabilities and overcome the outlined drawbacks, we introduce a model transformation framework that converts a Simulink model to an executable specification, written in an actor-oriented modeling language. This specification then serves as the input of an established Electronic System Level (ESL) design flow, enabling Design Space Exploration (DSE) and automatic code generation for both hardware and software. In this demonstration, we will show how to automatically transform Simulink models to an established ESL design flow by means of a code generator. Based on the generated code, we will present a co-simulation approach that combines complex environmental models from Matlab/Simulink with the auto-generated model of a controller. We will use an Anti-lock Braking System (ABS) as an example where we investigate the impact of different controller implementations in the automotive E/E architecture. In detail, the following scientific achievements are included in the proposed demonstration: To bridge Simulink and ESL design flows, we developed an ESL Code-Generator to perform model transformation. The idea is that for any given Simulink models such as a controller in a control system, the designer can simply invoke our Code-Generator to create the ESL model automatically. In our design flow, we use SystemC as a programming language with an extension of actors with a specific Model of Computation (MoC). We guarantee the preservation of the semantics of the generated model by (a) applying a specific 1-to-1 mapping from Simulink basic blocks to an actor library and (b) considering different transformations to capture single-rate and multi-rate Simulink models. After the model transformation is finished, this auto-generated SystemC model serves as the input of a well-established ESL design flow that enables DSE. Besides the Code-Generator we demonstrate also a validation technique that considers the functional correctness by comparing the original Simulink model with the generated SystemC model. The main idea behind this technique is (1) to co-simulate the auto-generated model along with the the original model and (2) to reuse the environment model and the test bench that are originally created in Simulink also for the auto-generated model. Furthermore, the performance of the model can also be measured during co-simulation. In this demonstration, an ABS model will be transformed from Simulink to SystemC by invoking ESL Code-Generator. Then, by applying our validation technique, the correctness and the accuracy of the auto-generated model can be examined. Lastly, to evaluate the performance of the model, application-depended quality of control will be measured, such as the braking distance on an icy road. More information ...
UB11.03	BICONDITIONAL BINARY DECISION DIAGRAM MANIPULATION PACKAGE Authors: Luca Amaru1, Alexios Balatsoukas-Stimming2, Pierre-Emmanuel Gaillardon3, Andreas Burg2 and Giovanni De Micheli3 1EPFL, CH; 2EPFL-TCL, CH; 3EPFL-LSI, CH Abstract In this software demonstration, we present a logic manipulation package based on Biconditional Binary Decision Diagrams (BBDDs). BBDDs are a novel class of canonical binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional on two variables. We show how Verilog files from real life designs can be rapidly read and processed by the BBDD manipulation package, for verification, testing or synthesis purposes. In particular, we demonstrate the benefit deriving from BBDD re-writing of arithmetic circuits in the synthesis of a product code iterative decoder. More information ...
UB11.04	HEROES^2: A SYSTEMC FRAMEWORK FOR MODELING, SIMULATION AND TESTING OF HETEROGENEOUS SOFTWARE-INTENSIVE SYSTEMS Authors: Markus Becker1, Wolfgang Mueller1, Ulrich Kiffmeier2 and Joachim Stroop2 1University of Paderborn/C-LAB, DE; 2dSPACE GmbH, DE Abstract HeroeS^2 is a SystemC framework for modeling/simulation of heterogeneous SW-intensive systems. It has 8 abstraction levels for corefinement of application/environment models from continous/discrete models to networked embedded SW stacks. Support of various SW/comm. abstractions is achieved by combining AMS MoCs, TLM, HdS models (MW, RTOS, HAL) and QEMU user mode/system emulator. Interfacing w/ a commerical AUTOSAR toolchain is provided, i.e., code generators, integration and experimentation tools. More information ...
UB11.05	RESCV: RESOURCE-AWARE COMPUTER VISION APPLICATION ON HETEROGENEOUS MULTI-TILE ARCHITECTURE Authors: Ericles Sousa1, Johny Paul2, Vahid Lari1, Frank Hannig1, Jürgen Teich1 and Walter Stechele2 1University of Erlangen-Nuremberg, DE; 2Technische Universität München, DE Abstract We demonstrate the benefits of invasive computing by showing the efficiency and utilization improvements in a resource-aware manner by algorithmic selection of different invasive resources, such as TCPA (tightly-coupled processor array), and RISC processors. More specific we present a dynamic load balancing of a computer vision application between multiple RISC cores and a TCPA, based on invasive mechanisms supported by our operating system and the agent system. More information ...
UB11.06	SKETCH-BASED ESL VIRTUAL PROTOTYPING: SKETCH-BASED DESIGN AND SIMULATION-BASED EVALUATION FOR ESL VIRTUAL PROTOTYPING Authors: Rafael Rosales1, Michael Glaß1, Jürgen Teich1, Bo Wang2, Yang Xu2 and Ralph Hasholzner2 1University of Erlangen-Nuremberg, DE; 2Intel Mobile Communications, DE Abstract Virtual prototyping and Electronic System Level (ESL) modeling have become valuable approaches to cope with the ever-increasing complexity of embedded systems. Their effectiveness, however, is highly dependent on their quick development time and accuracy both conflicting goals. In this demonstration, we present (a) an ESL methodology [1] [2] for the simulation-based evaluation of power and performance of embedded systems by the use of virtual prototypes. Our methodology permits us to develop ESL models for design space exploration of dynamic power and performance management strategies and hardware/software co-design choices. (b) We present a novel sketch-based tool termed Mahler [3] for the very early design phase of ESL modeling. Mahler provides a playground to quickly model functionality and evaluate performance on different architecture implementations. In Mahler, ESL models are created by literally sketching with a pen or touch interface, e.g. a tablet stylus, or a touchless interface, such as a Leap Motion controller. The application and architecture models are transformed to an executable virtual prototype through sketch recognition. This approach provides a very intuitive and fast way to explore actor-oriented functional modeling and hardware/software partitioning. The output of Mahler is a simulation-ready SystemC-based source-code stub that can be refined for subsequent design iterations. We will show a model of a Voice over LTE (VoLTE) use case, consisting of a heterogeneous cellular SoC platform, together with a wireless channel fading model and a base station network model. State-based [1] and polynomial-equation-based [4] power models are built and co-simulated for the SoC digital module and the RF transceiver module, respectively to abstract their different power consumption characterization accurately. The entire end-to-end modeling enables efficient SoC performance and power simulation with proper network configuration in seconds, which is highly desired in cellular system early design exploration phase and co-optimization with network vendors. More information ...
UB11.07	VERIFIC-MM Authors: Christoph Kuznik and Wolfgang Müller, University of Paderborn, DE Abstract Verific-MM is an approach to systematize and accelerate the coverage plan engineering as well as the verification environment's (functional) metric code generation -- usually a time-consuming and error-prone task -- in particular by (i) improving automation via assisted model-based approaches, utilizing recent industry standards such as UCIS and (ii) a supporting methodology suitable for various target (functional coverage) languages (IEEE-1800 SystemVerilog, IEEE-1647 e, IEEE-1666 SystemC). More information ...
16:30	End of session