Date: Wednesday 26 March 2014
Time: 14:00 - 16:00
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB07.01	VIDEO-BASED ABSOLUTE NAVIGATION APPROACH: A NOVEL APPROACH FOR VIDEO-BASED ABSOLUTE NAVIGATION IN SPACE EXPLORATION MISSIONS Authors: Pascal Trotta, Tadewos Getahun Tadewos, Paolo Prinetto, Daniele Rolfo and Pascal Trotta, Politecnico di Torino, IT Abstract Nowadays, space agencies have increased their research efforts in order to enhance the success rate of space exploration missions. Future space missions will increasingly adopt Video Based Navigation (VBN) systems to assist the entry, descent and landing (EDL) phase of space modules. This poster will show a preliminary work on a novel approach for Video-based Absolute Navigation (VBAN). Moreover, the poster depicts how a VBAN processing chain can exploit FPGA devices to achieve high throughput. Several visual results will be shown to highlight the peculiarities of the proposed approach. More information ...
UB07.02	AIDA: ANALOG IC DESIGN AUTOMATION Authors: Nuno Horta1, Nuno Lourenço2, Ricardo Martins2, Ricardo Póvoa2, António Canelas2 and Pedro Ventura1 1Instituto de Telecomunicacoes, PT; 2Instituto de Telecomunicacoes / Instituto Superior Técnico, PT Abstract This demonstration presents AIDA, an analog integrated circuit (IC) design automation environment. AIDA includes two main modules, namely, AIDA-C and AIDA-L. AIDA-C is a circuit-level synthesis tool which uses state-of-the-art multi-objective multi-constrained optimization kernels, based on evolutionary computation techniques, where the robustness of the solutions is attained by considering a layout-aware approach and, also, extreme process variations by means of PVT corner analysis. The circuit's performance is measured using Spectre®, ELDO® or HSPICE® electrical simulators as evaluation engines. AIDA-L considers the device sizes and the best floorplan, obtained with AIDA-C, and generates the complete layout by placing and routing the devices, while fulfilling the technology design rules by using built-in design-rule check (DRC) and layout-versus-schematic (LVS) procedures. In order to demonstrate AIDA design environment several analog circuit structures, e.g., OTAs, LNAs, LC-Oscillators, etc., will be synthesized in a 130nm CMOS technology. AIDA-C is demonstrated for circuit-level sizing and optimization by generating a family of Pareto Optimal solutions based on user performance and functional specifications. AIDA-L is demonstrated by generating the layout of a user selected solution from AIDA-C, taking into account electrical currents information to mitigate electromigration and IR-drop effects, and also wiring symmetry for multiport multi-terminal signal nets of analog ICs. More information ...
UB07.03	BICONDITIONAL BINARY DECISION DIAGRAM MANIPULATION PACKAGE Authors: Luca Amaru1, Alexios Balatsoukas-Stimming2, Pierre-Emmanuel Gaillardon3, Andreas Burg2 and Giovanni De Micheli3 1EPFL, CH; 2EPFL-TCL, CH; 3EPFL-LSI, CH Abstract In this software demonstration, we present a logic manipulation package based on Biconditional Binary Decision Diagrams (BBDDs). BBDDs are a novel class of canonical binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional on two variables. We show how Verilog files from real life designs can be rapidly read and processed by the BBDD manipulation package, for verification, testing or synthesis purposes. In particular, we demonstrate the benefit deriving from BBDD re-writing of arithmetic circuits in the synthesis of a product code iterative decoder. More information ...
UB07.04	GEMINI: A NEW SYNTHESIS AND OPTIMIZATION TOOL FOR GRAPHENE-BASED DIGITAL DEVICES Authors: Valerio Tenace, Andrea Calimera, Massimo Poncino and Enrico Macii, Politecnico di Torino, IT Abstract Gemini is a synthesis and optimization software for graphene-based digital devices. Given a combinational circuit description through its boolean representation, Gemini produces a SPICE netlist mapped with graphene PN-Junction gates. The software is composed of a parser library to handle input circuit descriptions, a characterization library of graphene gates used in the synthesis process, a Biconditional Binary Decision Diagram library used to manipulate logic networks in Pass-XNOR logic in order to better exploit the intrinsic characteristics of the adopted graphene gates, and a number of optimization algorithms designed to produce better results in terms of area and thus power consumption. As a stand-alone software or as a library easy to integrate into state-of-the-art tools, Gemini represents a first step of an enabling technology for future synthesis and optimization processes for graphene-based devices. More information ...
UB07.05	TOMAHAWK2: PERFORMANCE IMPACT OF INSTRUCTION SET ARCHITECTURE EXTENSIONS FOR DYNAMIC TASK SCHEDULING UNITS Author: Oliver Arnold, Technische Universität Dresden, DE Abstract In this demo a heterogeneous MPSoC is controlled by a dynamic task scheduling unit called CoreManager. The instruction set architecture of this unit has been extended to improve performance for dynamic data dependency checking, task scheduling, processing element allocation and data transfer management. The MPSoC as well as the NoC are integrated in a cycle-accurate virtual system prototype. The performance impact of the CoreManager is analyzed on component as well as on system level. More information ...
UB07.06	LEGO: TOOLS FOR HYBRID INTEGRATION Author: Fredrik Jonsson, Royal Institute of Technology, SE Abstract Performance of printed devices depends on the geometry, but is also affected by processing steps of other components integrated onto the same substrate. Since different designs use different devices, process stack, models and design rules must be dynamically determined. In this work we propose and demonstrate an experimental design flow to allow efficient design of hybrid and printed electronic circuits. More information ...
UB07.07	UVM-SYSTEMC-AMS: UVM STANDARD-COMPLIANT SYSTEMC (AMS)-BASED VERIFICATION FRAMEWORK FOR HETEROGENEOUS SYSTEMS Authors: Zhi Wang1, Yao Li2, Marie-Minerve Louerat2, Francois Pecheux2, Martin Barnasconi3, Thilo Vörtler4 and Karsten Einwich4 1Laboratoire d'informatique de Paris 6, FR; 2UPMC-LIP6, FR; 3NXP, NL; 4Fraunhofer IIS, DE Abstract Today's societal needs for innovative products in terms of communication, mobility, health, entertainment, and safety directly impact microelectronics design methodologies. The embedded systems are simultaneously software-driven, digitally assisted, complex and heterogeneous, but existing verification methodologies are mostly focused on pure digital devices and are completely decoupled from analog verification. This presentation shows how the principles of the new UVM methodology can be soundly enhanced to offer to the test designer a flexible framework for the virtual prototyping of multi-discipline testbenches that supports both digital and Analog Mixed-Signal (AMS) at the architectural level. More information ...
UB07.08	TTOOL/DIPLODOCUSDF: A UML ENVIRONMENT FOR HARDWARE/SOFTWARE CO-DESIGN OF DATA-DOMINATED SYSTEMS-ON-CHIP Authors: Andrea Enrici, Ludovic Apvrille and Renaud Pacalet, Telecom ParisTech, FR Abstract The development of new Systems on Chip commonly relies on previous products for whom, due to factors such as system complexities, time and cost constraints, little design space exploration can be performed. Hardware and software are typically composed as if they were separate components, whereas their interactions yield more than the sum of the two parts. In the scope of the demonstration, we present our enhanced version of TTool/DiplodocusDF, a UML model-driven engineering tool and methodology for the design of heterogeneous data processing systems. Our contributions enrich the modeling and design space exploration capabilities of TTool/DiplodocusDF to target complex transfer schemes and control information exchange at different abstraction levels. Our ameliorated methodology is applied to two signal processing applications, showing the analysis of novel interactions between typically conflicting aspects such as computations vs communications and dataflows vs controlflows. More information ...
UB07.09	A HOLISTIC APPROACH TO POWER MANAGEMENT FOR ENERGY HARVESTING EMBEDDED SYSTEMS Authors: Kyungsoo Lee, Hideki Takase and Tohru Ishihara, Kyoto University, JP Abstract We present a holistic approach to maximizing the energy efficiency of energy harvesting embedded systems which consist of a processor system and an energy harvesting system. A power management program integrated on a real-time OS optimally switches operation mode of the processor and configuration of the energy harvesting system according to the workload of the processor and harvesting situation. The demonstration will show that our prototype system consisting of our processor chip and harvesting system board stably runs using harvested energy only. The processor has multiple cores having a different performance in each to improve the energy efficiency of computation. The energy harvesting board has high transferring efficiency to reduce the power loss. The entire system is controlled efficiently by our power management program implemented on Toppers OS. More information ...
UB07.10	STMC TOOLS: A STATE TRANSITION MODEL DESCRIPTION LANGUAGE STMC AND ITS TOOLS - AN EXTENSION OF THE C PROGRAMMING LANGUAGE FOR DEVELOPING DRIVER SOFTWARE AND FIRMWARE WITH MODELS - Authors: Nobuhiko Ogura1, Ikuta Tanigawa2, Takuya Todoroki1, Kenji Arai1 and Harumi Watanabe2 1Tokyo City University, JP; 2Tokai University, JP Abstract We present a state transition model description programming language. It can be translated to pure standard C programs without any OS or handwritten frameworks, hence it is suit for developing low level driver software and firmware, unlike many other automatic software generation tools from software models that usually focuses on higher level models. We show the language and translator to executable software and visual diagram generator, and analysis tools, with embedded software examples. More information ...
16:00	End of session Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).