12.8 Panel: Future SoC verification methodology: UVM evolution or revolution?

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Date: Thursday 27 March 2014
Time: 16:00 - 17:30
Location / Room: Exhibition Theatre

Alex Goryachev, IBM Research - Haifa, IL

Rolf Drechsler, University of Bremen/DFKI, DE

It is a recent trend that SoCs are becoming more similar to servers. Many SoCs today are no longer tied to a single application and look more like general purpose PCs and high-end servers. Smartphones are the most notable example of this, but we are also seeing this with TV chips, in-car controllers, network routers, and more. This trend is occurring in parallel to the constantly growing complexity of SoCs, which support diverse IO interfaces and devices, and have complex architectures including multiple heterogeneous cores, multi-level caches, and multiple IO bridges. Today, common practice for verification is based on Universal Verification Methodology (UVM), which, at the system level, is built on reusing and combining unit-level environments, followed by running real software on an SoC. This methodology leaves a large gap. In high-end systems, this gap is covered by system-level verification that focuses on HW-only system integration. This level has its own methodology, dedicated environment, set of tools, and teams. It looks at the system as a whole and is not based on reusing lower level environments. Formal methods are a field of intensive research, but they have not been adopted by the industry for SoC-level verification. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology. Is the gap in today's SoC verification methodology significant? Is it growing? Or perhaps it does not exist? What is the right way to close the gap, if one exists? Is it sufficient to extend UVM capabilities (e.g., SystemC, TLM) or are dedicated tools and methodology needed? Are formal methods ready to play a significant role in SoC-level verification? In general, we would like to determine the importance of system-level verification and its unique needs—whether generators, checking, coverage, or teams.


  • Lyes Benalycherif, STMicroelectronics, FR
  • Franco Fummi, University of Verona, IT
  • Alan J. Hu, University of British Columbia, Vancouver, CA
  • Ronny Morad, IBM Research - Haifa, IL
  • Frank Schirrmeister, Cadence Design Systems, US
17:30End of session