DATE 2014 Awards Ceremony
DATE 2014 Best Paper Award
This year, the award committee decided to give one award per track.
The DATE 2014 Best Paper Awards are given to the following persons for their contributions as stated below.
Track D: System Specifications, Models, and Methodologies
May-Happen-in-Parallel Analysis based on Segment Graphs for Safe ESL Models
Weiwei Chen, Xu Han, Rainer Dömer, Center for Embedded Computer Systems, University of California, Irvine, US
Track A: Secure Systems
An Efficient Reliable PUF-Based Cryptographic Key Generator in 65nm CMOS
Mudit Bhargava, Ken Mai, Department of Electrical and Computer Engineering, Carnegie Mellon University, US
Track T: Test Generation, Simulation, Diagnosis and System Test
Efficient SMT-based ATPG for Interconnect Open Defects
Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker, University of Freiburg, DE
Track E: Model-based Design and Verification for Embedded Systems
Scalability Bottlenecks Discovery in MPSoC Platforms Using Data Mining on Simulation Traces
Sofiane Lagraa1,2, Alexandre Termier1, Frédéric Pétrot2
1LIG Laboratory, University Joseph Fourier, Grenoble, FR 2TIMA Laboratory, Grenoble Institute of Technology, Grenoble, FR
EDAA Outstanding Dissertation Award 2013
Category 1
Out-of-Order Parallel Simulation for Electronic System-Level Design
Weiwei Chen, The University of California, Irvine, US
Category 2
Design and Runtime Optimizations of Hybrid Electrical Energy Storage Systems
Younghyun Kim, Seoul National University, KR
Category 3
Design-Technology Co-Optimization in Next Generation Lithography
Hongbo Zhang, University of Illinois at Urbana-Champaign, US
Category 4
Online Self-Test, Diagnostics, and Self-Repair for Robust System Design
Yanjing Li, Stanford University, US
DATE 2014 Best IP Awards
Reducing Set-Associative L1 Data Cache Energy by Early Load Data Dependence Detection (ELD3)
Alen Bardizbanyan1, Magnus Själander2, David Whalley2 and Per Larsson-Edefors1
1Chalmers University of Technology, SE; 2Florida State University, US
Thermal Analysis and Model Identification Techniques for a Logic + WIDEIO Stacked DRAM Test Chip
Francesco Beneventi1, Andrea Bartolini1, Pascal Vivet2, Denis Dutoit2 and Luca Benini1
1DEI - University of Bologna, IT; 2CEA-Leti, Grenoble, FR
