Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Bayard

Chair:
Rob Aitken, ARM, US

Co-Chair:
Mehdi Tahoori, Karlsruhe Institute of Technology, DE

Papers in this session address a broad range of challenges which we face in advanced technologies: how NAND flash ages and how this can be measured, how to ensure high yield for SRAM by doing very effective simulations, and an adaptive self-calibrating synchronizer that can cope with supply voltage, temperature and process variation.

Time	Label	Presentation Title Authors
08:30	9.6.1	THRESHOLD VOLTAGE DISTRIBUTION IN MLC NAND FLASH MEMORY: CHARACTERIZATION, ANALYSIS AND MODELING Authors: Yu Cai1, Erich Haratsch2, Onur Mutlu1 and Ken Mai1 1DSSC, Carnegie Mellon University, US; 2LSI Corporation, US Abstract
09:00	9.6.2	EFFICIENT IMPORTANCE SAMPLING FOR HIGH-SIGMA YIELD ANALYSIS WITH ADAPTIVE ONLINE SURROGATE MODELING Authors: Jian Yao, Zuochang Ye and Yan Wang, Tsinghua University, CN Abstract
09:30	9.6.3	METASTABILITY CHALLENGES FOR 65NM AND BEYOND; SIMULATION AND MEASUREMENTS Authors: Salomon Beer1, Ran Ginosar1, Jerome Cox2, Tom Chaney2 and Davis M. Zar2 1Technion, IL; 2Blendics, US Abstract
10:00	IP4-21, 477	DESIGN AND IMPLEMENTATION OF AN ADAPTIVE PROACTIVE RECONFIGURATION TECHNIQUE FOR SRAM CACHES Authors: Peyman Pouyan, Esteve Amat, Francesc Moll and Antonio Rubio, Universitat Politècnica de Catalunya, ES Abstract
10:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.