Date: Thursday 21 March 2013
Time: 08:30 - 10:00
Location / Room: Meije

Chair:
Fresco Regazzoni, TU Delft / University of Lugano, CH

Co-Chair:
Patrick Schaumont, Virginia Tech, US

This session describes novel results in the manufacturing and operation of secure chips. The first paper addresses the risks in a secure manufacturing process, and presents a suitable countermeasure. A major risk in secure manufacturing is the insertion of hardware trojans in the design; the second and third paper describe detection techniques for such malicious insertions. The proposed techniques use delay measurements, and multi-modal characterization to achieve high detection probability despite the effects of manufacturing variation. An attacker may also target the design phase and steal intellectual property. The fourth paper introduces a reverse engineering technique to reconstruct a design from a low-level netlist. To answer these threats, we will need new tools and methods. The last paper in this session presents a design method to analyze timing-based security leaks in a design.

Time	Label	Presentation Title Authors
08:30	9.5.1	(Best Paper Award Candidate) IS SPLIT MANUFACTURING SECURE? Authors: Jeyavijayan Rajendran1, Ozgur Sinanoglu2 and Ramesh Karri1 1Polytechnic Institue of New York University, US; 2New York University - Abu Dhabi, AE Abstract
09:00	9.5.2	TROJAN DETECTION VIA DELAY MEASUREMENTS: A NEW APPROACH TO SELECT PATHS AND VECTORS TO MAXIMIZE EFFECTIVENESS AND MINIMIZE COST Authors: Byeongju Cha and Sandeep K. Gupta, University of Southern California, US Abstract
09:30	9.5.3	HIGH-SENSITIVITY HARDWARE TROJAN DETECTION USING MULTIMODAL CHARACTERIZATION Authors: Kangqiao Hu1, Abdullah N. Nowroz2, Sherief Reda2 and Farinaz Koushanfar1 1Rice University, US; 2Brown University, US Abstract
10:00	IP4-19, 474	REVERSE ENGINEERING DIGITAL CIRCUITS USING FUNCTIONAL ANALYSIS Authors: Pramod Subramanyan, Nestan Tsiskaridze, Kanika Pasricha, Dillon Reisman, Adriana Susnea and Sharad Malik, Princeton University, US Abstract
10:01	IP4-20, 181	A PRACTICAL TESTING FRAMEWORK FOR ISOLATING HARDWARE TIMING CHANNELS Authors: Jason Oberg1, Sarah Meiklejohn1, Timothy Sherwood2 and Ryan Kastner1 1University of California, San Diego, US; 2University of California, Santa Barbara, US Abstract
10:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.