7.6 On-Line Approaches Towards Processor Resilience

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Date: Wednesday 20 March 2013
Time: 14:30 - 16:00
Location / Room: Bayard

Chair:
Yiorgos Makris, University of Dallas, US

Co-Chair:
Xavier Vera, Intel, ES

This session brings the audience papers dealing with on-line detection and resilience for processors by task replication and redundant execution.

TimeLabelPresentation Title
Authors
14:307.6.1(Best Paper Award Candidate)
EFFICIENT SOFTWARE BASED FAULT TOLERANCE APPROACH ON MULTICORE PLATFORMS
Authors:
Hamid Mushtaq, Zaid Al-Ars and Koen Bertels, TU Delft, NL
Abstract
15:007.6.2USING EXPLICIT OUTPUT COMPARISONS FOR FAULT TOLERANT SCHEDULING (FTS) ON MODERN HIGH-PERFORMANCE PROCESSORS
Authors:
Yue Gao, Sandeep K. Gupta and Melvin Breuer, University of Southern California, US
Abstract
15:307.6.3LOW COST PERMANENT FAULT DETECTION USING ULTRA-REDUCED INSTRUCTION SET CO-PROCESSORS
Authors:
Sundaram Ananthanarayan1, Siddharth Garg2 and Hiren Patel2
1Stanford University, US; 2University of Waterloo, CA
Abstract
16:00IP3-21, 592IMPROVING FAULT TOLERANCE USING HARDWARE-SOFTWARE-CO-SYNTHESIS
Authors:
Heinz Riener1, Stefan Frehse1 and Goerschwin Fey2
1University Bremen, DE; 2German Aerospace Center, DE
Abstract
16:01IP3-22, 444A DYNAMIC SELF-ADAPTIVE CORRECTION METHOD FOR ERROR RESILIENT APPLICATION
Authors:
Luming Yan, Huaguo Liang and Zhengfeng Huang, Hefei University of Technology, CN
Abstract
16:00End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.