6.5 Reliable Multi-Processor Computing Systems Design

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Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Meije

Chair:
Jose Ayala, Complutense University of Madrid, ES

Co-Chair:
Christian Pilato, Politecnico di Milano, IT

This session tackles the problems of task mapping and allocation for latest multi-processor systems under possible error conditions. The first paper deals with task mapping to maximize the correct operation of multi-processor architectures under reliability constrained setups. The second paper proposes a new scheduling framework for processing systems that can adapt to different fault tolerance requirements. The third paper explores methods to use coarse-grained reconfigurable architectures in order to guarantee reliable system-level behavior, and the fourth paper explores the development of a configurable soft-error resilience approach to achieve reliable specific instruction-set processing architectures.

TimeLabelPresentation Title
Authors
11:006.5.1(Best Paper Award Candidate)
RELIABILITY-DRIVEN TASK MAPPING FOR LIFETIME EXTENSION OF NETWORKS-ON-CHIP BASED MULTIPROCESSOR SYSTEMS
Authors:
Anup Das, Akash Kumar and Bharadwaj Veeravalli, National University of Singapore, SG
Abstract
11:306.5.2A WORK-STEALING SCHEDULING FRAMEWORK SUPPORTING FAULT TOLERANCE
Authors:
Yizhuo Wang, Weixing Ji, Feng Shi and Qi Zuo, Beijing Institute of Technology, CN
Abstract
12:006.5.3A COST-EFFECTIVE SELECTIVE TMR FOR HETEROGENEOUS COARSE-GRAINED RECONFIGURABLE ARCHITECTURES BASED ON DFG-LEVEL VULNERABILITY ANALYSIS
Authors:
Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi and Takashi Sato, Kyoto University, JP
Abstract
12:156.5.4CSER: HW/SW CONFIGURABLE SOFT-ERROR RESILIENCY FOR APPLICATION SPECIFIC INSTRUCTION-SET PROCESSORS
Authors:
Tuo Li1, Muhammad Shafique2, Semeen Rehman2, Swarnalatha Radhakrishnan1, Roshan Ragel1, Jude Angelo Ambrose1, Jörg Henkel2 and Sri Parameswaran1
1University of New South Wales, AU; 2Karlsruhe Institute of Technology, DE
Abstract
12:30IP3-5, 101RELIABILITY ANALYSIS FOR INTEGRATED CIRCUIT AMPLIFIERS USED IN NEURAL MEASUREMENT SYSTEMS
Authors:
Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen and Steffen Paul, University of Bremen, DE
Abstract
12:31IP3-6, 271ON-LINE TESTING OF PERMANENT RADIATION EFFECTS IN RECONFIGURABLE SYSTEMS
Authors:
Luca Cassano1, Dario Cozzi2, Sebastian Korf2, Jens Hagemeyer2, Mario Porrmann2 and Luca Sterpone3
1University of Pisa, IT; 2Bielefeld University, DE; 3Politecnico di Torino, IT
Abstract
12:32IP3-7, 426AN APPROACH FOR REDUNDANCY IN FLEXRAY NETWORKS USING FPGA PARTIAL RECONFIGURATION
Authors:
Shanker Shreejith1, Kizheppatt Vipin1, Suhaib A Fahmy1 and Martin Lukasiewycz2
1Nanyang Technological University, SG; 2TUM CREATE, SG
Abstract
12:30End of session
Lunch Break in Ecrins
Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)