Date: Wednesday 20 March 2013
Time: 11:00 - 12:30
Location / Room: Stendahl

Chair:
Valeria Bertacco, University of Michigan, US

Co-Chair:
Elena Vatajelu, LIRMM, FR

With processor architectures becoming increasingly complex and concurrent, new verification ideas are needed to rescue them from being bug-ridden. This session addresses a number of key issues in this domain: simulation performance, correctness of concurrency, and of the models used to validate the software running on them. The session presents solutions to boost the performance of architectural simulators and cache simulation and to effectively verify memory transactions with respect to consistency.

Time	Label	Presentation Title Authors
11:00	6.3.1	ON-THE-FLY VERIFICATION OF MEMORY CONSISTENCY WITH CONCURRENT RELAXED SCOREBOARDS Authors: Leandro S. Freitas, Eberle A. Rambo and Luiz C. V. dos Santos, Federal University of Santa Catarina, BR Abstract
11:30	6.3.2	FAST CACHE SIMULATION FOR HOST-COMPILED SIMULATION OF EMBEDDED SOFTWARE Authors: Kun Lu, Daniel Mueller-Gritschneder and Ulf Schlichtmann, Technische Universität München, DE Abstract
12:00	6.3.3	A CRITICAL-SECTION-LEVEL TIMING SYNCHRONIZATION APPROACH FOR DETERMINISTIC MULTI-CORE INSTRUCTION-SET SIMULATIONS Authors: Fan-Wei Yu, Bo-Han Zeng, Yu-Hung Huang, Hsin-I Wu, Che-Rung Lee and Ren-Song Tsay, National Tsing Hua University, TW Abstract
12:15	6.3.4	MULTI-LEVEL PHASE ANALYSIS FOR SAMPLING SIMULATION Authors: Jiaxin Li1, Weihua Zhang1, Haibo Chen2 and Binyu Zang1 1Fudan University, CN; 2Shanghai Jiaotong University, CN Abstract
12:30	IP3-1, 232	HYPERVISED TRANSIENT SPICE SIMULATIONS OF LARGE NETLISTS & WORKLOADS ON MULTI-PROCESSOR SYSTEMS Authors: Grigorios Lyras, Dimitrios Rodopoulos, Antonis Papanikolaou and Dimitrios Soudris, NTUA-ECE-MicroLab, GR Abstract
12:30		End of session Lunch Break in Ecrins Sandwich lunch (Eat early for High-Performance Low-Power Computing - Energy Efficient Computing Keynote - Room Oisans at 1330; http://www.date-conference.com/conference/session/7.0)