Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Les Bans

Chair:
Björn Franke, University of Edinburgh, UK

Co-Chair:
Heiko Falk, Ulm University, DE

This session covers a broad spectrum of topics in compilers, software synthesis, validation, and transformation. The first paper addresses communication optimization for kernels offloaded to accelerators. It is followed by a paper focussing on concurrency in a synchronous model of computation. The third paper deals with source-level cache modelling. The fourth paper proposes the management of heap data of tasks which are executed on a multi-core architecture with limited local memory.

Time	Label	Presentation Title Authors
08:30	5.7.1	(Best Paper Award Candidate) OPTIMIZING REMOTE ACCESSES FOR OFFLOADED KERNELS: APPLICATION TO HIGH-LEVEL SYNTHESIS FOR FPGA Authors: Christophe Alias1, Alain Darte2 and Alexandru Plesco1 1INRIA, FR; 2CNRS, FR Abstract
09:00	5.7.2	SEQUENTIALLY CONSTRUCTIVE CONCURRENCY - A CONSERVATIVE EXTENSION OF THE SYNCHRONOUS MODEL OF COMPUTATION Authors: Reinhard von Hanxleden1, Michael Mendler2, Joaquin Aguado2, Björn Duderstadt1, Insa Fuhrmann1, Stephen Mercer3, Christian Motika1 and Owen O'Brien3 1Kiel University, DE; 2Bamberg University, DE; 3National Instruments, US Abstract
09:30	5.7.3	FAST AND ACCURATE CACHE MODELING IN SOURCE-LEVEL SIMULATION OF EMBEDDED SOFTWARE Authors: Zhonglei Wang and Jörg Henkel, Karlsruhe Institute of Technology, DE Abstract
09:45	5.7.4	AUTOMATIC AND EFFICIENT HEAP DATA MANAGEMENT FOR LIMITED LOCAL MEMORY MULTICORE ARCHITECTURES Authors: Ke Bai and Aviral Shrivastava, Arizona State University, US Abstract
10:00	IP2-12, 552	SOFTWARE ENABLED WEAR-LEVELING FOR HYBRID PCM MAIN MEMORY ON EMBEDDED SYSTEMS Authors: Jingtong Hu1, Qingfeng Zhuge2, Chun Xue3, Wei-Che Tseng1 and Edwin Sha1 1University of Texas at Dallas, US; 2Chongqing University, CN; 3City University of Hong Kong, HK Abstract
10:01	IP2-13, 240	PROBABILISTIC TIMING ANALYSIS ON CONVENTIONAL CACHE DESIGNS Authors: Leonidas Kosmidis1, Charlie Curtsinger2, Eduardo Quiñones3, Jaume Abella3, Emery Berger2 and Francisco Cazorla4 1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2University of Massachusetts Amherst, US; 3Barcelona Supercomputing Center, ES; 4Barcelona Supercomputing Center and IIIA-CSIC, ES Abstract
10:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.