Date: Wednesday 20 March 2013
Time: 10:00 - 10:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the morning. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

Label	Presentation Title Authors
IP2-1	AN EFFICIENT NETWORK ON-CHIP ARCHITECTURE BASED ON ISOLATING LOCAL AND NON-LOCAL COMMUNICATIONS Authors: Vahideh Akhlaghi1, Mehdi Kamal1, Ali Afzali-Kusha1 and Massoud Pedram2 1University of Tehran, IR; 2University of Southern California, US Abstract
IP2-2	SVR-NOC: A PERFORMANCE ANALYSIS TOOL FOR NETWORK-ON-CHIPS USING LEARNING-BASED SUPPORT VECTOR REGRESSION MODEL Authors: Zhiliang Qian1, Da-Cheng Juan2, Paul Bogdan2, Chi-Ying Tsui1, Diana Marculescu2 and Radu Marculescu2 1Hong Kong University of Science and Technology, HK; 2Carnegie Mellon University, US Abstract
IP2-3	FUTURE OF GPGPU MICRO-ARCHITECTURAL PARAMETERS Authors: Cedric Nugteren, Gert-Jan van den Braak and Henk Corporaal, Eindhoven University of Technology, NL Abstract
IP2-4	SYNCHRONIZING CODE EXECUTION ON ULTRA-LOW-POWER EMBEDDED MULTI-CHANNEL SIGNAL ANALYSIS PLATFORMS Authors: Ahmed Yasir Dogan, Jeremy Constantin, Ruben Braojos Lopez, Giovanni Ansaloni, Andreas Burg and David Atienza, EPFL, CH Abstract
IP2-5	USING SYNCHRONIZATION STALLS IN POWER-AWARE ACCELERATORS Authors: Ali Jooya and Amirali Baniasadi, The University of Victoria, CA Abstract
IP2-6	MEMRISTOR PUFS: A NEW GENERATION OF MEMORY-BASED PHYSICALLY UNCLONABLE FUNCTIONS Authors: Unal Kocabas1, Patrick Koeberl2 and Ahmad-Reza Sadeghi3 1Technische Universität Darmstadt, DE; 2Intel Corporation, DE; 3Technische Universität Darmstadt and Fraunhofer SIT Darmstadt, DE Abstract
IP2-7	WIRELESS SENSOR NETWORK SIMULATION FOR SECURITY AND PERFORMANCE ANALYSIS Authors: Álvaro Díaz1, Pablo Sanchez1, Juan Sancho2 and Juan Rico2 1University of Cantabria, ES; 2TST, ES Abstract
IP2-8	PROCESS-VARIATION-AWARE IDDQ DIAGNOSIS FOR NANO-SCALE CMOS DESIGNS - THE FIRST STEP Authors: Chia-Ling (Lynn) Chang1, Charles H.-P. Wen1 and Jayanta Bhadra2 1National Chiao Tung University, TW; 2Freescale, US Abstract
IP2-9	AUTOMATED DETERMINATION OF TOP LEVEL CONTROL SIGNALS Authors: Rohit Jain, Praveen Tiwari and Soumen Ghosh, Synopsys, IN Abstract
IP2-10	AN EFFICIENT AND FLEXIBLE HARDWARE SUPPORT FOR ACCELERATING SYNCHRONIZATION OPERATIONS ON THE STHORM MANY-CORE ARCHITECTURE Authors: Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe and Raphael David, CEA LIST, FR Abstract
IP2-11	ELECTRICAL CALIBRATION OF SPRING-MASS MEMS CAPACITIVE ACCELEROMETERS Authors: Lingfei Deng1, Vinay Kundur1, Naveen Sai Jangala Naga1, Muhlis Kenan Ozel1, Ender Yilmaz1, Sule Ozev1, Bertan Bakkaloglu1, Sayfe Kiaei1, Divya Pratab2 and Tehmoor Dar2 1Arizona State University, US; 2Freescale, US Abstract
IP2-12	SOFTWARE ENABLED WEAR-LEVELING FOR HYBRID PCM MAIN MEMORY ON EMBEDDED SYSTEMS Authors: Jingtong Hu1, Qingfeng Zhuge2, Chun Xue3, Wei-Che Tseng1 and Edwin Sha1 1University of Texas at Dallas, US; 2Chongqing University, CN; 3City University of Hong Kong, HK Abstract
IP2-13	PROBABILISTIC TIMING ANALYSIS ON CONVENTIONAL CACHE DESIGNS Authors: Leonidas Kosmidis1, Charlie Curtsinger2, Eduardo Quiñones3, Jaume Abella3, Emery Berger2 and Francisco Cazorla4 1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2University of Massachusetts Amherst, US; 3Barcelona Supercomputing Center, ES; 4Barcelona Supercomputing Center and IIIA-CSIC, ES Abstract