5.4 Novel Approaches for Real-Time Architectures

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Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Chartreuse

Chair:
Cristina Silvano, Politecnico di Milano, IT

Co-Chair:
Andreas Moshovos, University of Toronto , CA

This section focuses on new approaches for real-time architectures that go beyond classic static approaches. The first paper presents the first practical, effective, and efficient cache design that enables probabilistic worst-case execution time analysis. The second paper presents a novel architecture that enables fast and time-predictable computation for switched hybrid automata, a new modelling framework for power electronics applications. The third paper presents a conservative open-page memory controller policy that improves average-case performance without sacrificing worst-case time guarantees.

TimeLabelPresentation Title
Authors
08:305.4.1A CACHE DESIGN FOR PROBABILISTICALLY ANALYSABLE REAL-TIME SYSTEMS
Authors:
Leonidas Kosmidis1, Jaume Abella2, Eduardo Quiñones2 and Francisco J. Cazorla3
1Barcelona Supercomputing Center and Universitat Politècnica de Catalunya, ES; 2Barcelona Supercomputing Center, ES; 3CSIC and BSC-CNS, ES
Abstract
09:005.4.2MARTHA: ARCHITECTURE FOR CONTROL AND EMULATION OF POWER ELECTRONICS AND SMART GRID SYSTEMS
Authors:
Michel Kinsy1, Omer Khan2, Ivan Celanovic1 and Srinivas Devadas1
1MIT, US; 2University of Connecticut, US
Abstract
09:305.4.3CONSERVATIVE OPEN-PAGE POLICY FOR MIXED TIME-CRITICALITY MEMORY CONTROLLERS
Authors:
Sven Goossens1, Benny Akesson2 and Kees Goossens1
1Eindhoven University of Technology, NL; 2Polytechnic Institute of Porto, PT
Abstract
10:00IP2-10, 274AN EFFICIENT AND FLEXIBLE HARDWARE SUPPORT FOR ACCELERATING SYNCHRONIZATION OPERATIONS ON THE STHORM MANY-CORE ARCHITECTURE
Authors:
Farhat Thabet, Yves Lhuillier, Caaliph Andriamisaina, Jean-Marc Philippe and Raphael David, CEA LIST, FR
Abstract
10:00End of session
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