Date: Wednesday 20 March 2013
Time: 08:30 - 10:00
Location / Room: Stendahl

Chair:
Jaan Raik, Tallinn University of Technology, EE

Co-Chair:
Adrian Evans, iRoC Technologies, FR

It is becoming increasingly difficult to fully verify an SoC prior to tape-out resulting in more debug work occurring after first silicon. In the past, the techniques for post-silicon debug were largely ad-hoc. This session includes papers which highlight a new, emerging body of work which applies advanced algorithms to obtain optimized hardware for post-silicon debug. The first paper describes a new technique for selecting an optimal set of trace signals using a mixture of fast metrics and simulation profiling. In the second paper, the authors apply anomaly detection algorithms similar to those used for fraud detection to the automatic temporal and spatial localization of bugs. The third paper presents a low-area hardware block which can be used to reduce the volume of data that needs to be exported when dumping cache contents in the lab. The final paper tackles a slightly different, but very important aspect of silicon validation problem and proposes an innovative technique to perform BER estimation on high-speed links.

Time	Label	Presentation Title Authors
08:30	5.3.1	A HYBRID APPROACH FOR FAST AND ACCURATE TRACE SIGNAL SELECTION FOR POST-SILICON DEBUG Authors: Min Li and Azadeh Davoodi, University of Wisconsin - Madison, US Abstract
09:00	5.3.2	MACHINE LEARNING-BASED ANOMALY DETECTION FOR POST-SILICON BUG DIAGNOSIS Authors: Andrew DeOrio1, Qingkun Li2, Matthew Burgess1 and Valeria Bertacco1 1University of Michigan, US; 2University of Illinois at Urbana-Champaign, US Abstract
09:15	5.3.3	SPACE SENSITIVE CACHE DUMPING FOR POST-SILICON VALIDATION Authors: Sandeep Chandran, Smruti R. Sarangi and Preeti Ranjan Panda, Indian Institute of Technology Delhi, IN Abstract
09:30	5.3.4	FAST AND ACCURATE BER ESTIMATION METHODOLOGY FOR I/O LINKS BASED ON EXTREME VALUE THEORY Authors: Alessandro Cevrero1, Nestor Evmorfopoulos2, Charalampos Antoniadis2, Paolo Ienne1, Yusuf Leblebici1, Andreas Burg1 and George Stamoulis2 1EPFL, CH; 2University of Thessaly, GR Abstract
10:00	IP2-9, 481	AUTOMATED DETERMINATION OF TOP LEVEL CONTROL SIGNALS Authors: Rohit Jain, Praveen Tiwari and Soumen Ghosh, Synopsys, IN Abstract
10:00		End of session Coffee Break in Exhibition Hall Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.