4.6 New Techniques for Test Pattern Generation
Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Bayard
Chair:
Sudhakar Reddy, University of Iowa, US
Co-Chair:
Matteo Sonza Reorda, Politecnico di Torino, IT
The session presents new test pattern generation methods for low power memory cells as well as for dealing with unknown values and delay faults.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.6.1 | (Best Paper Award Candidate) ACCURATE QBF-BASED TEST PATTERN GENERATION IN PRESENCE OF UNKNOWN VALUES Authors: Stefan Hillebrecht1, Michael A. Kochte2, Dominik Erb1, Hans-Joachim Wunderlich2 and Bernd Becker1 1University of Freiburg, DE; 2University of Stuttgart, DE Abstract |
| 17:30 | 4.6.2 | TEST SOLUTION FOR DATA RETENTION FAULTS IN LOW-POWER SRAMS Authors: Leonardo Henrique Bonet Zordan1, Alberto Bosio1, Patrick Girard1, Luigi Dilillo1, Aida Todri-Sanial1, Arnaud Virazel1 and Nabil Badereddine2 1LIRMM, FR; 2Intel Mobile Communications, FR Abstract |
| 18:00 | 4.6.3 | EFFICIENT SAT-BASED DYNAMIC COMPACTION AND RELAXATION FOR LONGEST SENSITIZABLE PATHS Authors: Matthias Sauer1, Sven Reimer1, Tobias Schubert1, Ilia Polian2 and Bernd Becker1 1University of Freiburg, DE; 2University of Passau, DE Abstract |
| 18:30 | IP2-8, 23 | PROCESS-VARIATION-AWARE IDDQ DIAGNOSIS FOR NANO-SCALE CMOS DESIGNS - THE FIRST STEP Authors: Chia-Ling (Lynn) Chang1, Charles H.-P. Wen1 and Jayanta Bhadra2 1National Chiao Tung University, TW; 2Freescale, US Abstract |
| 18:30 | End of session Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall |
