4.4 Emerging Solutions to Manage Energy/Performance Trad-Offs Along the Memory Hierarchy
Date: Tuesday 19 March 2013
Time: 17:00 - 18:30
Location / Room: Chartreuse
Chair:
Mladen Berekovic, Technical University of Braunschweig, DE
Co-Chair:
Cristina Silvano, Politecnico di Milano, IT
The session discusses emerging solutions to efficiently manage energy/performance trade-offs along the memory hierarchy from caches to secondary storage solutions. The first paper proposes a multiple access cache interface to provide low energy. The second paper introduces an efficient RAM management technique for NAND flash-based storage systems, while the third paper describes a data protection technique for NAND flash storage systems. The fourth paper proposes how to exploit sub-arrays inside a bank to improve the performance of Phase Change Memory, a promising alternative or supplement to DRAM.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 17:00 | 4.4.1 | MALEC: A MULTIPLE ACCESS LOW ENERGY CACHE Authors: Matthias Boettcher1, Giacomo Gabrielli2, Bashir M. Al-Hashimi1 and Danny Kershaw3 1University of Southampton, UK; 2ARM, UK; 3NXP Semiconductors, AT Abstract |
| 17:30 | 4.4.2 | TREEFTL: EFFICIENT RAM MANAGEMENT FOR HIGH PERFORMANCE OF NAND FLASH-BASED STORAGE SYSTEMS Authors: Chundong Wang and Weng-Fai Wong, National University of Singapore, SG Abstract |
| 18:00 | 4.4.3 | DA-RAID-5: A DISTURB AWARE DATA PROTECTION TECHNIQUE FOR NAND FLASH STORAGE SYSTEMS Authors: Jie Guo1, Wujie Wen1, Yaojun Zhang1, Sicheng Li2, Hai Li1 and Yiran Chen1 1University of Pittsburgh, US; 2Polytechnic Institute of New York University, US Abstract |
| 18:15 | 4.4.4 | EXPLOITING SUBARRAYS INSIDE A BANK TO IMPROVE PHASE CHANGE MEMORY PERFORMANCE Authors: Jianhui Yue and Yifeng Zhu, University of Maine, US Abstract |
| 18:30 | IP2-3, 697 | FUTURE OF GPGPU MICRO-ARCHITECTURAL PARAMETERS Authors: Cedric Nugteren, Gert-Jan van den Braak and Henk Corporaal, Eindhoven University of Technology, NL Abstract |
| 18:31 | IP2-4, 638 | SYNCHRONIZING CODE EXECUTION ON ULTRA-LOW-POWER EMBEDDED MULTI-CHANNEL SIGNAL ANALYSIS PLATFORMS Authors: Ahmed Yasir Dogan, Jeremy Constantin, Ruben Braojos Lopez, Giovanni Ansaloni, Andreas Burg and David Atienza, EPFL, CH Abstract |
| 18:32 | IP2-5, 329 | USING SYNCHRONIZATION STALLS IN POWER-AWARE ACCELERATORS Authors: Ali Jooya and Amirali Baniasadi, The University of Victoria, CA Abstract |
| 18:30 | End of session Evening Reception offered by the City of Grenoble in Several serving points inside the Exhibition Hall |
