3.6 Dealing with Timing Variation in Advanced Technologies

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Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Bayard

Chair:
Bram Kruseman, NXP, NL

Co-Chair:
Saqib Khursheed, University of Southampton, UK

To get the best performance one needs to minimize slack, however, this is getting challenging since one needs to take into account many aspects. The papers in this session present the benefits of taking aging into account during the design phase, how to measure in-situ the slack, and test pattern generation that takes into account statistical variation to improve coverage.

TimeLabelPresentation Title
Authors
14:303.6.1(Best Paper Award Candidate)
MTTF-BALANCED PIPELINE DESIGN
Authors:
Fabian Oboril and Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Abstract
15:003.6.2EFFICIENT VARIATION-AWARE STATISTICAL DYNAMIC TIMING ANALYSIS FOR DELAY TEST APPLICATIONS
Authors:
Marcus Wagner and Hans-Joachim Wunderlich, University of Stuttgart, DE
Abstract
15:303.6.3SLACKPROBE: A LOW OVERHEAD IN SITU ON-LINE TIMING SLACK MONITORING METHODOLOGY
Authors:
Liangzhen Lai1, Vikas Chandra2, Rob Aitken2 and Puneet Gupta1
1University of California, Los Angeles, US; 2ARM, US
Abstract
16:00IP1-18, 224CAPTURING POST-SILICON VARIATIONS BY LAYOUT-AWARE PATH-DELAY TESTING
Authors:
Xiaolin Zhang, Jing Ye, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
16:01IP1-19, 678ADAPTIVE REDUCTION OF THE FREQUENCY SEARCH SPACE FOR MULTI-VDD DIGITAL CIRCUITS
Authors:
Chandra Suresh1, Ender Yilmaz2, Ozgur Sinanoglu1 and Sule Ozev3
1NYU Abu Dhabi, AE; 2Freescale, US; 3Arizona State University, US
Abstract
16:00End of session
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