3.4 Microarchitectural Techniques for Reliability

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Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Chartreuse

Chair:
Todd Austin, Michigan University Ann Arbor, US

Co-Chair:
Mladen Berekovic, Technical University of Braunschweig, DE

This session introduces a variety of papers regarding reliability issues, which are managed by fault tolerance, fault avoidance, and error correction techniques. The first paper proposes to aggressively utilize computation results from error-prone processors. The second one tries to avoid voltage drops in multi-core processors by focusing on the inter-core power interactions. The third and fourth papers propose error detection and correction techniques; the former one is for memories and the latter one for logic circuits.

TimeLabelPresentation Title
Authors
14:303.4.1EXTRACTING USEFUL COMPUTATION FROM ERROR-PRONE PROCESSORS FOR STREAMING APPLICATIONS
Authors:
Yavuz Yetim, Margaret Martonosi and Sharad Malik, Princeton University, US
Abstract
15:003.4.2ORCHESTRATOR: A LOW-COST SOLUTION TO REDUCE VOLTAGE EMERGENCIES FOR MULTI-THREADED APPLICATIONS
Authors:
Xing Hu, Guihai Yan, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN
Abstract
15:303.4.3MEMORY ARRAY PROTECTION: CHECK ON READ OR CHECK ON WRITE?
Authors:
Panagiota Nikolaou1, Yanos Sazeides1, Lorena Ndreou1, Emre Ozer2 and Sachin Idgunji3
1University of Cyprus, CY; 2ARM, UK; 3ARM, US
Abstract
15:453.4.4FAULTM: ERROR DETECTION AND RECOVERY USING HARDWARE TRANSACTIONAL MEMORY
Authors:
Gulay Yalcin, Osman Unsal and Adrian Cristal, Barcelona Supercomputing Center, ES
Abstract
16:00IP1-13, 674PHOENIX: REVIVING MLC BLOCKS AS SLC TO EXTEND NAND FLASH DEVICES LIFETIME
Authors:
Xavier Jimenez, David Novo and Paolo Ienne, École Polytechnique Fédérale de Lausanne, CH
Abstract
16:00End of session
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