Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Chartreuse

Chair:
Georgi Gaydadjiev, Chalmers University of Technology, SE

Co-Chair:
Todd Austin, Michigan University Ann Arbor, US

This session covers memory architectures to improve energy efficiency, reliability, performance, and access patterns in caches. The first paper proposes a mechanism to overcome sensitivity to access-time variations in L1 cache. The second paper introduces a new memory-addressing method and corresponding coherency protocol to handle two-dimensional memory access patterns. The third paper suggests a hybrid cache architecture composed of a hybrid SRAM and DRAM caches instead of two separate cache levels to reduce inter-core DRAM interferences. The last paper in the session uses a combination of SRAM and eDRAM to build energy-efficient L1 data caches that are resilient to errors when operating at near-threshold voltages.

Time	Label	Presentation Title Authors
11:30	2.4.1	(Best Paper Award Candidate) AVICA: AN ACCESS-TIME VARIATION INSENSITIVE L1 CACHE ARCHITECTURE Authors: Seokin Hong and Soontea Kim, Korea Advanced Institute of Science and Technology, KR Abstract
12:00	2.4.2	DUAL-ADDRESSING MEMORY ARCHITECTURE FOR TWO-DIMENSIONAL MEMORY ACCESS PATTERNS Authors: Yen-Hao Chen and Yi-Yu Liu, Yuan Ze University, TW Abstract
12:30	2.4.3	ADAPTIVE CACHE MANAGEMENT FOR A COMBINED SRAM AND DRAM CACHE HIERARCHY FOR MULTI-CORES Authors: Fazal Hameed, Lars Bauer and Jörg Henkel, Karlsruhe Institute of Technology, DE Abstract
12:45	2.4.4	COMBINING RAM TECHNOLOGIES FOR HARD-ERROR RECOVERY IN L1 DATA CACHES WORKING AT VERY-LOW POWER MODES Authors: Vicente Lorente1, Alejandro Valero1, Julio Sahuquillo1, Salvador Petit1, Ramón Canal2, Pedro López1 and José Duato1 1Universitat Politècnica de València, ES; 2Universitat Politècnica de Catalunya, ES Abstract
13:00	IP1-6, 967	A DUAL GRAIN HIT-MISS DETECTOR FOR LARGE DIE-STACKED DRAM CACHES Authors: Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos, University of Toronto, CA Abstract
13:01	IP1-7, 233	REDUCING WRITES IN PHASE-CHANGE MEMORY ENVIRONMENTS BY USING EFFICIENT CACHE REPLACEMENT POLICIES Authors: Roberto Rodriguez, Fernando Castro, Daniel Chaver, Luis Pinuel and Francisco Tirado, Complutense University, ES Abstract
13:00		End of session Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)