Date: Tuesday 19 March 2013
Time: 11:30 - 13:00
Location / Room: Belle-Etoile

Chair:
Alper Sen, Bogazici University, TR

Co-Chair:
Daniel Grosse, University of Bremen, DE

The session is centered around parallelization and verification of electronic designs during simulation. The first paper introduces an optimization technique for out-of-order parallel discrete event simulation of ESL designs using static analysis of potential hazards at compile time. The second paper describes a new way of parallelizing loosely-timed SystemC models using primitives that can explicitly capture durations for tasks. The third paper presents trade-offs estimation of fixed-point errors on linear time-invariant systems by combining advantages of statistical and analytical techniques. The final paper proposes a run-time algorithm to verify design properties of non-linear analogue circuits using efficient data structures.

Time	Label	Presentation Title Authors
11:30	2.2.1	(Best Paper Award Candidate) OPTIMIZED OUT-OF-ORDER PARALLEL DISCRETE EVENT SIMULATION USING PREDICTIONS Authors: Weiwei Chen and Rainer Doemer, University of California, Irvine, US Abstract
12:00	2.2.2	PARALLEL PROGRAMMING WITH SYSTEMC FOR LOOSELY TIMED MODELS: A NON-INTRUSIVE APPROACH Author: Matthieu Moy, Grenoble University (Grenoble INP, Verimag), FR Abstract
12:30	2.2.3	ACCURACY VS SPEED TRADEOFFS IN THE ESTIMATION OF FIXED-POINT ERRORS ON LINEAR TIME-INVARIANT SYSTEMS Authors: David Novo1, Sara El Alaoui2 and Paolo Ienne1 1EPFL, CH; 2Al Akhawayn University, MA Abstract
12:45	2.2.4	RUNTIME VERIFICATION OF NONLINEAR ANALOG CIRCUITS USING INCREMENTAL TIME-AUGMENTED RRT ALGORITHM Authors: Seyed Nematollah Ahmadyan, Jayanand Asok Kumar and Shobha Vasudevan, University of Illinois at Urbana-Champaign, US Abstract
13:00	IP1-1, 933	AN AUTOMATED PARALLEL SIMULATION FLOW FOR HETEROGENEOUS EMBEDDED SYSTEMS Authors: Seyed Hosein Attarzadeh Niaki and Ingo Sander, KTH Royal Institute of Technology, SE Abstract
13:01	IP1-2, 354	MUTATION ANALYSIS WITH COVERAGE DISCOUNTING Authors: Peter Lisherness, Nicole Lesperance and Kwang-Ting Cheng, University of California, Santa Barbara, US Abstract
13:02	IP1-3, 772	SCALABLE FAULT LOCALIZATION FOR SYSTEMC TLM DESIGNS Authors: Hoang M. Le, Daniel Große and Rolf Drechsler, University of Bremen, DE Abstract
13:00		End of session Lunch Break in Auditorium Dauphine (Lunch and Learn Session) and Ecrins Sandwich lunch in both locations (Lunch and Learn Session Sponsored by Mentor Graphics: "Grenoble Ecosystem to Provide Semiconductor Alternative Process for Advanced CMOS - 1300-1400 hrs; http://www.date-conference.com/conference/session/3.0)