11.2 High-Level Synthesis and Coarse-Grained Reconfigurable Architectures

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Date: Thursday 21 March 2013
Time: 14:00 - 15:30
Location / Room: Belle-Etoile

Chair:
Philippe Coussy, Université de Bretagne-Sud, FR

Co-Chair:
Fadi Kurdahi, University of California Irvine, US

The first paper investigates the impact of simultaneous scheduling and binding in high-level synthesis. The second paper improves latency by performing high-level code transformation with Taylor Expansion Diagrams. The thirth paper presents a platform based on custom reconfigurable arrays for multi-processor systems exploiting instruction- and thread-level parallelism.The fourth paper proposes a high-level modelling tool chain for embedded FPGAs.

TimeLabelPresentation Title
Authors
14:0011.2.1SHARE WITH CARE: A QUANTITATIVE EVALUATION OF SHARING APPROACHES IN HIGH-LEVEL SYNTHESIS
Authors:
Alex Kondratyev, Luciano Lavagno, Mike Meyer and Yosinori Watanabe, Cadence Design Systems, US
Abstract
14:3011.2.2FPGA LATENCY OPTIMIZATION USING SYSTEM-LEVEL TRANSFORMATIONS AND DFG RESTRUCTURING
Authors:
Daniel Gomez-Prado, Maciej Ciesielski and Russell Tessier, University of Massachusetts Amherst, US
Abstract
14:4511.2.3A TRANSPARENT AND ENERGY AWARE RECONFIGURABLE MULTIPROCESSOR PLATFORM FOR SIMULTANEOUS ILP AND TLP EXPLOITATION
Authors:
Mateus Rutzig1, Antonio Carlos Schneider Beck2 and Luigi Carro2
1Federal University of Santa Maria, BR; 2Federal University of Rio Grande do Sul, BR
Abstract
15:0011.2.4HIGH-LEVEL MODELING AND SYNTHESIS FOR EMBEDDED FPGAS
Authors:
Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid and Tobias Noll, RWTH Aachen University, DE
Abstract
15:30IP5-11, 851SCHEDULING INDEPENDENT LIVENESS ANALYSIS FOR REGISTER BINDING IN HIGH LEVEL SYNTHESIS
Authors:
Vito Giovanni Castellana and Fabrizio Ferrandi, Politecnico di Milano, IT
Abstract
15:31IP5-12, 60FAST SHARED ON-CHIP MEMORY ARCHITECTURE FOR EFFICIENT HYBRID COMPUTING WITH CGRAS
Authors:
Jongeun Lee, Yeonghun Jeong and Sungsok Seo, UNIST, KR
Abstract
15:32IP5-13, 59COMPILING CONTROL-INTENSIVE LOOPS FOR CGRAS WITH STATE-BASED FULL PREDICATION
Authors:
Kyuseung Han1, Jongeun Lee2 and Kiyoung Choi1
1Seoul National University, KR; 2UNIST, KR
Abstract
15:30End of session
Coffee Break in Exhibition Hall
Monday and Friday morning and afternoon coffee breaks will be located in the Salle de Reception. On Tuesday-Thursday the breaks will be located in the Exhibition Hall. Morning and afternoon (with the exception of Thursday afternoon which is a 30 minute break) coffee breaks on Tuesday-Thursday are extended breaks and will run for 60 minutes (coffee points will be open for the first 30 minutes only) from the start time indicated in the programme.