Date: Thursday 21 March 2013
Time: 15:30 - 16:00
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the afternoon. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

Label	Presentation Title Authors
IP5-1	MITIGATING DARK SILICON PROBLEMS USING SUPERLATTICE-BASED THERMOELECTRIC COOLERS Authors: Francesco Paterna and Sherief Reda, Brown University, US Abstract
IP5-2	RUN-TIME PROBABILISTIC DETECTION OF MISCALIBRATED THERMAL SENSORS IN MANY-CORE SYSTEMS Authors: Jia Zhao, Shiting (Justin) Lu, Wayne Burleson and Russell Tessier, University of Massachusetts Amherst, US Abstract
IP5-3	FORMAL ANALYSIS OF STEADY STATE ERRORS IN FEEDBACK CONTROL SYSTEMS USING HOL-LIGHT Authors: Osman Hasan and Muhammad Ahmad, National University of Sciences and Technology, PK Abstract
IP5-4	A NOVEL CONCURRENT CACHE-FRIENDLY BINARY DECISION DIAGRAM CONSTRUCTION FOR MULTI-CORE PLATFORMS Authors: Mahmoud El-Bayoumi1, Michael Hsiao1 and Mustafa ElNainay2 1Virginia Tech, US; 2Alexanderia University, EG Abstract
IP5-5	STATISTICAL MODELING WITH THE VIRTUAL SOURCE MOSFET MODEL Authors: Li Yu1, Lan Wei1, Dimitri Antoniadis1, Ibrahim Elfadel2 and Duane Boning1 1Massachusetts Institute of Technology, US; 2Masdar Institute of Science and Technology, AE Abstract
IP5-6	AUTOMATIC CIRCUIT SIZING TECHNIQUE FOR THE ANALOG CIRCUITS WITH FLEXIBLE TFTS CONSIDERING PROCESS VARIATION AND BENDING EFFECTS Authors: Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu and Chien-Nan Jimmy Liu, National Central University, TW Abstract
IP5-7	AN ENHANCED DOUBLE-TSV SCHEME FOR DEFECT TOLERANCE IN 3D-IC Authors: Hsiu-Chuan Shih and Cheng-Wen Wu, National Tsing Hua University, TW Abstract
IP5-8	MEMPACK: AN ORDER OF MAGNITUDE REDUCTION IN THE COST, RISK, AND TIME FOR MEMORY COMPILER CERTIFICATION Authors: Kartik Mohanram1, Matthew Wartell1 and Sundar Iyer2 1University of Pittsburgh, US; 2Memoir Systems, US Abstract
IP5-9	EXPLOITING REPLICATED CHECKPOINTS FOR SOFT ERROR DETECTION AND CORRECTION Authors: Fahrettin Koc, Kenan Bozdas, Burak Karsli and Oguz Ergin, TOBB University of Economics and Technology, TR Abstract
IP5-10	AN INTEGRATED APPROACH FOR MANAGING THE LIFETIME OF FLASH-BASED SSDS Authors: Sungjin Lee, Taejin Kim, Ji-Sung Park and Jihong Kim, Seoul National University, KR Abstract
IP5-11	SCHEDULING INDEPENDENT LIVENESS ANALYSIS FOR REGISTER BINDING IN HIGH LEVEL SYNTHESIS Authors: Vito Giovanni Castellana and Fabrizio Ferrandi, Politecnico di Milano, IT Abstract
IP5-12	FAST SHARED ON-CHIP MEMORY ARCHITECTURE FOR EFFICIENT HYBRID COMPUTING WITH CGRAS Authors: Jongeun Lee, Yeonghun Jeong and Sungsok Seo, UNIST, KR Abstract
IP5-13	COMPILING CONTROL-INTENSIVE LOOPS FOR CGRAS WITH STATE-BASED FULL PREDICATION Authors: Kyuseung Han1, Jongeun Lee2 and Kiyoung Choi1 1Seoul National University, KR; 2UNIST, KR Abstract
IP5-14	FAULT-TOLERANT ROUTING ALGORITHM FOR 3D NOC USING HAMILTONIAN PATH STRATEGY Authors: Masoumeh Ebrahimi, Masoud Daneshtalab and Juha Plosila, University of Turku, FI Abstract
IP5-15	MODELING AND ANALYSIS OF FAULT-TOLERANT DISTRIBUTED MEMORIES FOR NETWORKS-ON-CHIP Authors: Abbas BanaiyanMofrad1, Gustavo Girão2 and Nikil Dutt1 1University of California, Irvine, US; 2Federal University of Rio Grande do Sul, BR Abstract
IP5-16	HYBRID PROTOTYPING OF MULTICORE EMBEDDED SYSTEMS Authors: Ehsan Saboori and Samar Abdi, Concordia University, CA Abstract
IP5-17	LARGE-SCALE FLIP-CHIP POWER GRID REDUCTION WITH GEOMETRIC TEMPLATES Author: Zhuo Feng, Michigan Technological University, US Abstract
IP5-18	A NETWORK-FLOW BASED ALGORITHM FOR POWER DENSITY MITIGATION AT POST-PLACEMENT STAGE Authors: Sean Shih-Ying Liu, Ren-Guo Luo and Hung-Ming Chen, National Chiao Tung University, TW Abstract
IP5-19	AN EFFICIENT WIRELENGTH MODEL FOR ANALYTICAL PLACEMENT Authors: B.N.B. Ray and Shankar Balachandran, Indian Institute of Technology Madras, IN Abstract