Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node
Jan Lappas1,a, Andre Chinazzo1,b, Christian Weis1,c, Chenyang Xia2,e, Zhihang Wu2,f, Leibin Ni2,g and Norbert Wehn1,d
1Technische Universität Kaiserslautern, Germany
alappas@eit.uni-kl.de
bchinazzo@eit.uni-kl.de
cweis@eit.uni-kl.de
dwehn@eit.uni-kl.de
2Huawei Technologies Co., Ltd. Shenzhen, China
exiachenyang1@huawei.com
fwuzhihang@huawei.com
gnileibin@huawei.com
ABSTRACT
With the slow-down of Moore’s law and the increasing requirements on energy efficiency, alternative logic styles compared to complementary static CMOS have to be revisited for digital circuit implementations. Pass Transistor Logic (PTL) gained much attention in the ‘90s, however, only a limited number of recent investigations and publications regarding PTL exist that use advanced technology nodes. This paper compares key performance metrics of 22 different PTL based 1-bit full adder designs to a complementary static CMOS logic reference, using a recent 12nm FinFET technology. The figures of merit are the propagation delay, the energy consumption, and the energy-delay-product (EDP). Our investigations show that PTL based adder circuits can have an up to 49% decreased delay and a 48% and 63% reduced energy consumption and EDP, respectively, compared to a state-of-the-art complementary CMOS logic reference. In addition, we analyzed the impact of PVT variations on the delay for selected PTL full adder designs.
