DATE 2022 Best Papers                                                                         

•  The DATE 2022 Best Papers

•  Best Paper Award Nominations

DATE Best Paper Awards

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs, Lejla Batina, Theocharis Theocharides, Ilia Polian and Liliana Cucu and the following members: Steve Dai, Julien Forget Stefano Di Carlo, Elena Gnani, Sebastien Le Beux, Romain Lemaire, Hai Li, Nele Mentens, Maria Michael, Katell Morin-Allory, Gianluca Palermo, Ioannis Papaefstathiou, Christian Pilato, Davide Quaglia, Abbas Rahimi, Francesco Regazzoni, Ahmed Rezine, Rosa Rodrigues, Mohamed Sabri, Peh Li Shiuan, Lukas Sekanina, Olivier Sentieys, Johanna Sepulveda, Nima Taheri Nejad, Marian Verhelst, Arnaud Virazel, Pascal Vivet.

The DATE 2022 best papers are:

D Track

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler
Siting Liu¹, Peiyu Liao¹, Rui Zhang², Zhitang Chen³, Wenlong Lv³, Yibo Lin⁴, Bei Yu^1
1The Chinese University of Hong Kong, ²HiSilicon Technologies Co., Ltd. Shenzhen, ³Huawei Noah's Ark Lab, ⁴Peking University

A Track

Algorithm-Hardware Co-Design for Efficient Brain-Inspired Hyperdimensional Learning on Edge
Yang Ni¹, Yeseong Kim², Tajana Rosing³, Mohsen Imani^1
1University of California Irvine, ²DGIST Republic of Korea, ³University of California San Diego

T Track

Self-Terminated Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, Li Jiang
Shanghai Jiao Tong University, China

E Track

Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network Encoding
Zhilu Wang¹, Chao Huang², Qi Zhu^1
1Northwestern University, ²University of Liverpool

Best Paper Award Nominations

D Track

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
Zhe Lin¹, Zike Yuan², Jieru Zhao³, Wei Zhang⁴, Hui Wang¹, Yonghong Tian^5,1
1Peng Cheng Laboratory, ²The University of Auckland, ³Shanghai Jiao Tong University, ⁴Hong Kong University of Science and Technology, ⁵Peking University

PIMProf: An Automated Program Profiler for Processing-in-Memory Offloading Decisions
Yizhou Wei¹, Minxuan Zhou², Sihang Liu¹, Korakit Seemakhupt¹, Tajana Rosing², Samira Khan^1
1University of Virginia, ²University of California, San Diego

Full-credit Flow Control: A Novel Technique to Implement Deadlock-free Adaptive Routing
Yi Dai, Kai Lu, Sheng Ma, Junsheng Chang
National University of Defense Technology, China

FastGR : Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler
Siting Liu¹, Peiyu Liao¹, Rui Zhang², Zhitang Chen³, Wenlong Lv³, Yibo Lin⁴, Bei Yu^1
1The Chinese University of Hong Kong, ²HiSilicon Technologies Co., Ltd. Shenzhen, ³Huawei Noah's Ark Lab, ⁴Peking University

CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance
Lokesh Siddhu, Rajesh Kedia, Preeti Ranjan Panda
Indian Institute of Technology Delhi

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
Matheus Cavalcante¹, Anthony Agnesina², Samuel Riedel¹, Moritz Brunion³, Alberto Garcia-Ortiz³, Dragomir Milojevic⁴, Francky Catthoor⁴, Sung Kyu Lim², Luca Benini^5,1
1ETH Zurich, ²Georgia Tech, ³University of Bremen, ⁴IMEC, ⁵Università di Bologna

AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs
Guilherme Korol¹, Michael Jordan¹, Mateus Beck Rutzig², Antonio Carlos Schneider Beck^1
1Universidade Federal do Rio Grande do Sul, ²UFSM

Cross-Layer Approximation For Printed Machine Learning Circuits
Giorgos Armeniakos¹, Georgios Zervakis², Dimitrios Soudris¹, Mehdi Tahoori², Joerg Henkel^2
1National Technichal University of Athens, ²Karlsruhe Institute of Technology

A Track

Prefender: Prefetching Defender against Cache Side Channel Attacks as A Pretender
Luyi Li¹, Jiayi Huang², Lang Feng¹, Zhongfeng Wang^1
1Nanjing University, ²University of California, Santa Barbara

Algorithm-Hardware Co-Design for Efficient Brain-Inspired Hyperdimensional Learning on Edge
Yang Ni¹, Yeseong Kim², Tajana Rosing¹, Mohsen Imani^1
1University of California, Irvine, ²DGIST, Republic of Korea

Bioformers: Embedding Transformers for Ultra-Low Power sEMG-based Gesture Recognition
Alessio Burrello¹, Francesco Bianco Morghet², Moritz Scherer³, Simone Benatti¹, Luca Benini^1,3, Enrico Macii², Massimo Poncino², Daniele Jahier Pagliari^2
1Università di Bologna, ²Politecnico di Torino, ³ETH Zurich

Adaptive Droplet Routing for MEDA Biochips via Deep Reinforcement Learning
Mahmoud Elfar, Tung-Che Liang, Krishnendu Chakrabarty, Miroslav Pajic
Duke University

Accurate Probabilistic Miss Ratio Curve Approximation for Adaptive Cache Allocation in Block Storage Systems
Rongshang Li¹, Yingtian Tang², Qiquan Shi³, Hui Mao³, Lei Chen³, Jikun Jin⁴, Peng Lu⁴, Zhuo Cheng⁴,
¹University of Sydney, ²University of Pennsylvania, ³Huawei Noah's Ark Lab, ⁴Huawei Storage Product Line

T Track

ADD-based Spectral Analysis of Probing Security
Maria Chiara Molteni¹, Vittorio Zaccaria², Valentina Ciriani^1
1Universita' degli Studi di Milano, ²Politecnico di Milano

Are Analytical Techniques Worthwhile for Analog IC Placement?
Yishuang Lin¹, Yaguang Li¹, Donghao Fang¹, Meghna Madhusudan², Sachin S. Sapatnekar², Ramesh Harjani², Jiang Hu^1
1Texas A&M University, ²University of Minnesota

A Cross-Platform Cache Timing Attack Framework via Deep Learning
Ruyi Ding, Ziyue Zhang, Xiang Zhang, Cheng Gongye, Yunsi Fei, A. Adam Ding
Northeastern University

Self-Terminated Write of Multi-Level Cell ReRAM for Efficient Neuromorphic Computing
Zongwu Wang, Zhezhi He, Rui Yang, Shiquan Fan, Jie Lin, Fangxin Liu, Yueyang Jia, Chenxi Yuan, Qidong Tang, Li Jiang
Shanghai Jiao Tong University, China

Do Temperature and Humidity Exposures Hurt or Benefit Your SSDs?
Adnan Maruf¹, Sashri Brahmakshatriya¹, Baolin Li², Devesh Tiwari², Gang Quan¹, Janki Bhimani¹,
¹Florida International University, ²Northeastern University

E Track

DTQAtten: Leveraging Dynamic Token-based Quantization for Efficient Attention Architecture
Tao Yang, Dongyue Li, Zhuoran Song, Yilong Zhao, Fangxin Liu, Zongwu Wang, Zhezhi He, Li Jiang
Shanghai Jiao Tong University

MU-RMW: MiNIMIZING Unnecessary RMW Operations in the Embedded Flash with SMR Disk
Chenlin Ma, Zhuokai Zhou, Yingping Wang, Yi Wang, Rui Mao
Shenzhen University

GraphHD: Efficient graph classification using hyperdimensional computing
Igor Nunes, Mike Heddes, Tony Givargis, Alex Nicolau, Alex Veidenbaum
University of California, Irvine

AnaCoNGA: Analytical HW-CNN Co-design using Nested Genetic Algorithms
Nael Fasfous¹, Manoj Rohit Vemparala², Alexander Frickenstein², Emanuele Valpreda³, Driton Salihu¹, Julian Hofer⁴, Anmol Singh², Naveen-Shankar Nagaraja², Hans-Joerg Voegel², Nguyen Anh Vu Doan¹, Maurizio Martina³, Juergen Becker⁴, Walter Stechele^1
1Technical University of Munich, ²BMW AG, ³Politecnico di Torino, ⁴Karlsruhe Institute of Technology

Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network Encoding
Zhilu Wang¹, Chao Huang², Qi Zhu^1
1Northwestern University, ²University of Liverpool

Cache-Aware Schedulability Analysis of PREM Compliant Tasks
Syed Aftab Rashid¹, Muhammad Ali Awan¹, Pedro Souto², Konstantinos Bletsas¹, Eduardo Tovar^1
1CISTER, ISEP Polytechnic Institute of Porto, ²Faculty of Engineering of the University of Porto