Triple-Skipping Near-MRAM Computing Framework for AIoT Era
Juntong Chena, Hao Caib, Bo Liuc and Jun Yangd
National ASIC System Engineering Research Center Southeast University Nanjing, China
ajtchen@seu.edu.cn
bhao.cai@seu.edu.cn
cliubo_cnasic@seu.edu.cn
ddragon@seu.edu.cn
ABSTRACT
Near memory computing (NMC) paradigm shows great significance in non-von Neumann architecture to reduce data movement. The normally-off and instance-on characteristics of spin-transfer torque magnetic random access memory (STTMRAM) promise energy-efficient storage in the AIoT era. To avoid unnecessary memory-related processing, we propose a novel write-read-calculation triple-skipping (TS) NMC for multiplyaccumulate (MAC) operation with minimally modified peripheral circuits. The proposed TS-NMC is evaluated with a custom micro control unit (MCU) in 28-nm high-K metal gate (HKMG) CMOS process and foundry announced universal two-transistor twomagnetic tunnel junction (2T-2MTJ) MRAM cell. The framework consists of a sparse flag which is defined in extra STT-MRAM columns with only 0.73% area overhead, and a calculation block for NMC logic with 9.9% overhead. The TS-NMC can successfully work at 0.6-V supply voltage under 20MHz. This Near-MRAM framework can offer up to ∼95.6% energy saving compared to framework can offer up to ∼95.6% energy saving compared to commercial SRAM refer to ultra-low-power benchmark (ULPBenchmark). Classification task on MNIST takes 13nJ/pattern. The energy access of memory, calculation, and the total can be reduced by 52.49×, 2.7×, and 11.3× respectively from the TS scheme.
Keywords: STT-MRAM, near memory computing, neural network, MAC, triple-skipping, AIoT.
