DATE 2017 Best Papers

• The DATE 2017 Best Papers

• Best Paper Award Nominations

DATE Best Paper Awards

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee.

The DATE 2017 best papers are:

D Track

Automatic Place-and-Route of Emerging LED-Driven Wires within a Monolithically-Integrated CMOS+III-V Process
Tushar Krishn ³, Arya Balachandran¹, Siau Ben Chiah², Li Zhang³, Bing Wang³, Cong Wang², Kenneth Lee Eng Kian³, Jurgen Michel⁴, Li-Shiuan Peh⁴
¹ Georgia Institute of Technology, ² NTU, ³ SMART LEES, ⁴ National University of Singapore

A Track

CoSyn: Efficient Single-Cell Analysis Using a Hybrid Microfluidic Platform
Mohamed Ibrahim¹, Krishnendu Chakrabarty¹ , Ulf Schlichtmann²
¹ Duke University, ² Technical University of Munich

T Track

Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG
Jan Burchard¹, Dominik Erb¹, Adit D. Singh², Sudhakar M. Reddy³, Bernd Becker¹
¹ University of Freiburg, ² Auburn University, ³ University of Iowa

E Track

MoDNN: Local Distributed Mobile Computing System for Deep Neural Network
Jiachen Mao¹, Xiang Chen², Kent W. Nixon¹, Christopher Krieger³, Yiran Chen¹
¹ University of Pittsburgh, ² George Mason University, ³ University of Maryland

Best Paper Award Nominations

D track

Sampling-Based Binary-Level Cross-Platform Performance Estimation
Xinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John, Andreas Gerstlauer
The University of Texas at Austin

Optimizing Temperature Guardbands
Hussam Amrouch¹, Behnam Khaleghi², Joerg Henkel¹
¹ Karlsruhe Institute of Technology, ² Sharif University of Technology

Performance Impacts and Limitations of Hardware Memory-Access Trace Collection
Nicholas C. Doyle¹, Eric Matthews¹, Graham Holland¹, Alexandra Fedorova², Lesley Shannon¹
¹ Simon Fraser University, ² University of British Columbia

Reliability Assessment of Fault Tolerant Routing Algorithms in Networks-onChip: An Analytic Approach
Sadia Moriam and Gerhard Fettweis
TU Dresden

STAxCache: An Approximate, Energy Efficient STT -MRAM Cache
Ashish Ranjan¹, Swagath Venkataramani¹, Zoha Pajouhi¹, Rangharajan Venkatesan², Kaushik Roy¹, Anand Raghunathan¹
¹ Purdue University, ² NVIDIA Research

Shared Last-level Cache Management for GPGPUs with Hybrid Main Memory
Guan Wang, Xiaojun Cai, Lei Ju, Chuanqi Zang, Mengying Zhao, Zhiping Jia
Shandong University

An Efficient Leakage-Aware Thermal Simulation Approach for 3D-ICs Using Corrected Linearized Model and Algebraic Multigrid
Chao Yan¹, Hengliang Zhu¹, Dian Zhou², Xuan Zeng¹
¹ Fudan University, ² University of Texas at Dallas

Automating the Pipeline of Arithmetic Datapaths
Matei Istoan¹ and Florent de Dinechin²
¹ INRIA, ² INSA-Lyon

A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration
Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz Jr., Yiorgos Makris, Carl Sechen
The University of Texas at Dallas

Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing
Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili-Amiri, Kang L. Wang, Puneet Gupta
University of California, Los Angeles

A track

Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding
Walaa EI-Harouni, Semeen Rehman¹, Bharath Srinivas Prabakaran¹, Akash Kumar¹, Rehan Hafiz², Muhammad Shafique³
¹ TU Dresden, ² National University of Science and Technology Islamabad, ³ Vienna University of Technology (TU Wien)

Adaptive Compressed Sensing at the Fingertip of Internet-of-Things Sensors: An Ultra-Low Power Activity Recognition
Ramin Fallahzadeh¹, Josue Pagan Ortis², Hassan Ghasemzadeh¹
¹ Washington State University, ² Complutense University of Madrid

On Reducing Busy Waiting in AUTOSAR via Task-Release-Delta-based Runnable Reordering
Robert Höttger¹, Burkhard Igel¹, Olaf Spinczyk²
¹ FH-Dortmund, ² TU-Dortmund

Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip
Thorben Moos, Amir Morad, Bastian Richter
Ruhr-Universitat Bochum

T track

MVP ECC : Manufacturing Process Variation Aware Unequal Protection ECC for Memory Reliability
Seungyeob Lee and Joon-Sung Yang
Sungkyunkwan University

On the Limits of Machine Learning-Based Test: a Calibrated Mixed-Signal System Case Study
Manuel Barragan¹, Gildas Leger², Antonio Gines², Eduardo Peralias², Adoracion Rueda²
¹ TIMA Laboratory, ² CSIC - Universidad de Sevilla

E Track

Scalable Probabilistic Power Budgeting for Many-Cores
Anuj Pathania¹, Heba Khdr 1 -, Muhammad Shafique², Tulika Mitra ³, Joerg Henkel¹
¹ Karlsruhe Institute of Technology (KIT), ² Vienna University of Technology (TU Wien), ³ National University of Singapore