DATE 2017 Best Papers                                                                         

  The DATE 2017 Best Papers   Best Paper Award Nominations

DATE Best Paper Awards

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee.

The DATE 2017 best papers are:

D Track

Automatic Place-and-Route of Emerging LED-Driven Wires within a Monolithically-Integrated CMOS+III-V Process
Tushar Krishn 3, Arya Balachandran1, Siau Ben Chiah2, Li Zhang3, Bing Wang3, Cong Wang2, Kenneth Lee Eng Kian3, Jurgen Michel4, Li-Shiuan Peh4
1 Georgia Institute of Technology, 2 NTU, 3 SMART LEES, 4 National University of Singapore

A Track

CoSyn: Efficient Single-Cell Analysis Using a Hybrid Microfluidic Platform
Mohamed Ibrahim1, Krishnendu Chakrabarty1 , Ulf Schlichtmann2
1 Duke University, 2 Technical University of Munich

T Track

Fast and Waveform-Accurate Hazard-Aware SAT-Based TSOF ATPG
Jan Burchard1, Dominik Erb1, Adit D. Singh2, Sudhakar M. Reddy3, Bernd Becker1
1 University of Freiburg, 2 Auburn University, 3 University of Iowa

E Track

MoDNN: Local Distributed Mobile Computing System for Deep Neural Network
Jiachen Mao1, Xiang Chen2, Kent W. Nixon1, Christopher Krieger3, Yiran Chen1
1 University of Pittsburgh, 2 George Mason University, 3 University of Maryland

Best Paper Award Nominations

D track

Sampling-Based Binary-Level Cross-Platform Performance Estimation
Xinnian Zheng, Haris Vikalo, Shuang Song, Lizy K. John, Andreas Gerstlauer
The University of Texas at Austin

Optimizing Temperature Guardbands
Hussam Amrouch1, Behnam Khaleghi2, Joerg Henkel1
1 Karlsruhe Institute of Technology, 2 Sharif University of Technology

Performance Impacts and Limitations of Hardware Memory-Access Trace Collection
Nicholas C. Doyle1, Eric Matthews1, Graham Holland1, Alexandra Fedorova2, Lesley Shannon1
1 Simon Fraser University, 2 University of British Columbia

Reliability Assessment of Fault Tolerant Routing Algorithms in Networks-onChip: An Analytic Approach
Sadia Moriam and Gerhard Fettweis
TU Dresden

STAxCache: An Approximate, Energy Efficient STT -MRAM Cache
Ashish Ranjan1, Swagath Venkataramani1, Zoha Pajouhi1, Rangharajan Venkatesan2, Kaushik Roy1, Anand Raghunathan1
1 Purdue University, 2 NVIDIA Research

Shared Last-level Cache Management for GPGPUs with Hybrid Main Memory
Guan Wang, Xiaojun Cai, Lei Ju, Chuanqi Zang, Mengying Zhao, Zhiping Jia
Shandong University

An Efficient Leakage-Aware Thermal Simulation Approach for 3D-ICs Using Corrected Linearized Model and Algebraic Multigrid
Chao Yan1, Hengliang Zhu1, Dian Zhou2, Xuan Zeng1
1 Fudan University, 2 University of Texas at Dallas

Automating the Pipeline of Arithmetic Datapaths
Matei Istoan1 and Florent de Dinechin2
1 INRIA, 2 INSA-Lyon

A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration
Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz Jr., Yiorgos Makris, Carl Sechen
The University of Texas at Dallas

Hybrid VC-MTJ/CMOS Non-volatile Stochastic Logic for Efficient Computing
Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili-Amiri, Kang L. Wang, Puneet Gupta
University of California, Los Angeles

A track

Embracing Approximate Computing for Energy-Efficient Motion Estimation in High Efficiency Video Coding
Walaa EI-Harouni, Semeen Rehman1, Bharath Srinivas Prabakaran1, Akash Kumar1, Rehan Hafiz2, Muhammad Shafique3
1 TU Dresden, 2 National University of Science and Technology Islamabad, 3 Vienna University of Technology (TU Wien)

Adaptive Compressed Sensing at the Fingertip of Internet-of-Things Sensors: An Ultra-Low Power Activity Recognition
Ramin Fallahzadeh1, Josue Pagan Ortis2, Hassan Ghasemzadeh1
1 Washington State University, 2 Complutense University of Madrid

On Reducing Busy Waiting in AUTOSAR via Task-Release-Delta-based Runnable Reordering
Robert Höttger1, Burkhard Igel1, Olaf Spinczyk2
1 FH-Dortmund, 2 TU-Dortmund

Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip
Thorben Moos, Amir Morad, Bastian Richter
Ruhr-Universitat Bochum

T track

MVP ECC : Manufacturing Process Variation Aware Unequal Protection ECC for Memory Reliability
Seungyeob Lee and Joon-Sung Yang
Sungkyunkwan University

On the Limits of Machine Learning-Based Test: a Calibrated Mixed-Signal System Case Study
Manuel Barragan1, Gildas Leger2, Antonio Gines2, Eduardo Peralias2, Adoracion Rueda2
1 TIMA Laboratory, 2 CSIC - Universidad de Sevilla

E Track

Scalable Probabilistic Power Budgeting for Many-Cores
Anuj Pathania1, Heba Khdr 1 -, Muhammad Shafique2, Tulika Mitra 3, Joerg Henkel1
1 Karlsruhe Institute of Technology (KIT), 2 Vienna University of Technology (TU Wien), 3 National University of Singapore