Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
Mustafa Altun1, Valentina Ciriani2 and Mehdi Tahoori3
1Dept. of Electronics and Communication Engineering, Istanbul Technical University, Turkey.
altunmus@itu.edu.tr
2Dipartimento di Informatica, Universitá degli Studi di Milano, Italy.
valentina.ciriani@unimi.it
3Karlsruhe Institute of Technology, Karlsruhe, Germany.
tahoori@ira.uka.de
ABSTRACT
Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures, and can be fabricated such that each crosspoint can be used as a conventional electronic component such as a diode, a FET, or a switch. This is a unique opportunity that allows us to integrate well developed conventional circuit design techniques into nano-crossbar arrays. Motivated by this, our project aims to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. First two work packages of the project are presented in this paper. These packages are on logic synthesis that aims to implement Boolean functions with nanocrossbar arrays with area optimization, and fault tolerance that aims to provide a full methodology in the presence of high fault densities and extreme parametric variations in nano-crossbar architectures.
