Automating the Pipeline of Arithmetic Datapaths

Matei Istoan and Florent de Dinechin
Univ Lyon, Inria, INSA Lyon, CITI, F-69621 Villeurbanne, France


This article presents the new framework for semiautomatic circuit pipelining that will be used in future releases of the FloPoCo generator. From a single description of an operator or datapath, optimized implementations are obtained automatically for a wide range of FPGA targets and a wide range of frequency/latency trade-offs. Compared to previous versions of FloPoCo, the level of abstraction has been raised, enabling easier development, shorter generator code, and better pipeline optimization. The proposed approach is also more flexible than fully automatic pipelining approaches based on retiming: In the proposed technique, the incremental construction of the pipeline along with the circuit graph enables architectural design decisions that depend on the pipeline.

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